Bug 6750 - Intel PCI bridges are subtractive but don't report it...
Summary: Intel PCI bridges are subtractive but don't report it...
Alias: None
Product: xorg
Classification: Unclassified
Component: Server/DDX/Xorg (show other bugs)
Version: git
Hardware: x86 (IA32) Linux (All)
: high normal
Assignee: Adam Jackson
QA Contact:
Keywords: patch
: 5443 (view as bug list)
Depends on:
Blocks: 5041
  Show dependency treegraph
Reported: 2006-04-26 14:16 UTC by Dave Airlie
Modified: 2006-04-28 15:33 UTC (History)
5 users (show)

See Also:
i915 platform:
i915 features:

patch to fix Intel bridges (1.88 KB, patch)
2006-04-26 14:17 UTC, Dave Airlie
no flags Details | Splinter Review

Description Dave Airlie 2006-04-26 14:16:52 UTC
The Linux kernel has a quirk for the Intel PCI-PCI bridges in the chipsets which
report as normal bridges but in fact are subtractive / transparent bridges..

X.org messes up some memory decision because it doesn't know this.
Comment 1 Dave Airlie 2006-04-26 14:17:54 UTC
Created attachment 5478 [details] [review]
patch to fix Intel bridges

This patch detects the PCI bridges concerened, it also removes the BIOS range
from the sys reserved ranges, as Linux doesn't report this, in fact it should
really use the E820 table to figure it out, or better yet X shouldn't do any of
this on Linux...
Comment 2 Dave Airlie 2006-04-26 21:35:30 UTC
talked on IRC to Egbert, checked into HEAD.

Ajax you might want to consider this for 7.1, the top bit at least, for
dual-card setups.
Comment 3 Egbert Eich 2006-04-26 21:43:00 UTC
Patch looks OK. 
I'm not particularly fond of having to blacklist things in the code but the
broken HW is to blame here.
The BIOS range seems to be a legacy from some old HW. I don't have a strong
opinion on this.
Comment 4 Alan Hourihane 2006-04-26 21:43:05 UTC
*** Bug 5443 has been marked as a duplicate of this bug. ***
Comment 5 greg 2006-04-27 01:30:08 UTC
Would this affect me? I have an intel bridge but I don't understand what the 
pci_device&0xff00==0x2400 test does:

0000:00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev c2) (prog-if 
00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR+ FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR-
	Latency: 0
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=64
	I/O behind bridge: 0000c000-0000dfff
	Memory behind bridge: efe00000-f7efffff
	Prefetchable memory behind bridge: e7b00000-efbfffff
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
Comment 6 Adam Jackson 2006-04-29 00:59:03 UTC
top bit definitely looks good for 7.1.

would like a stronger vote either way on the bios range tweak.
Comment 7 Adam Jackson 2006-04-29 08:33:27 UTC
i lie.  applied to 7.1 branch, thanks!

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