Atom platforms began asserting with series ending in: ---------------------------------------------- b44c9292b7e5a24e6b06a197d4e72b43a8799d09 Author: Ian Romanick <ian.d.romanick@intel.com> intel/compiler: Don't handle fsign.sat No shader-db or CI changes on any Intel platform. ---------------------------------------------- stdout: /tmp/build_root/m64/lib/piglit/bin/shader_runner /tmp/build_root/m64/lib/piglit/tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/vs-sign-sat-neg-abs.shader_test -auto -fbo ---------------------------------------------- stderr: shader_runner: ../src/intel/compiler/brw_fs_generator.cpp:2477: int fs_generator::generate_code(const cfg_t*, int): Assertion `validated' failed. ---------------------------------------------- Unfortunately, atom systems are too slow to check patches pre-merge in CI. More specific bisection results should be available in a few hours.
The only patch that could have caused this is the one already identified, so you won't need to bisect.
Surprisingly, the first failure is one commit earlier: a68dd47b911053995ae387afcdc7fffe82e57420 Author: Ian Romanick <ian.d.romanick@intel.com> nir/algebraic: Simplify fsat of fsign These allows us to not support fsign.sat in the Intel compiler backend, and that will simplify some later changes. No shader-db changes on any Intel platform. I failed to notice that both the vs and fs variants of the test are broken.
To my surprise, the culprit is: commit a68dd47b911053995ae387afcdc7fffe82e57420 Author: Ian Romanick <ian.d.romanick@intel.com> Date: Sun Sep 9 13:40:02 2018 -0700 nir/algebraic: Simplify fsat of fsign These allows us to not support fsign.sat in the Intel compiler backend, and that will simplify some later changes. No shader-db changes on any Intel platform. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Thomas Helland <thomashelland90@gmail.com> Looking at the output from the EU validator, I think the problem is the b2f generates a 32-bit result instead of a 64-bit result: Native code for unnamed vertex shader GLSL3 SIMD8 shader: 35 instructions. 0 loops. 188 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 560 to 464 bytes (17%) START B0 (188 cycles) mov(8) g8<1>Q 0Q { align1 1Q }; mov(8) g119<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g120<1>F g4<8,8,1>F { align1 1Q compacted }; mov(8) g121<1>F g5<8,8,1>F { align1 1Q compacted }; mov(8) g122<1>F g6<8,8,1>F { align1 1Q compacted }; mov(8) g123<1>F g7<8,8,1>F { align1 1Q compacted }; mov(8) g126<1>F [0F, 0F, 0F, 0F]VF { align1 1Q compacted }; mov(8) g127<1>F 1F { align1 1Q }; cmp.l.f0(8) g4<1>DF g8<4,4,1>DF -(abs)g2<0,1,0>DF { align1 1Q }; cmp.l.f0(8) g6<1>DF g8<4,4,1>DF -(abs)g2.1<0,1,0>DF { align1 1Q }; cmp.l.f0(8) g10<1>DF g8<4,4,1>DF -(abs)g2.2<0,1,0>DF { align1 1Q }; cmp.l.f0(8) g12<1>DF g8<4,4,1>DF -(abs)g2.3<0,1,0>DF { align1 1Q }; mov(8) g4<1>D g4<8,4,2>UD { align1 1Q }; mov(8) g7<1>D g6<8,4,2>UD { align1 1Q }; mov(8) g2<1>D g10<8,4,2>UD { align1 1Q }; mov(8) g5<1>DF -g4<4,4,1>D { align1 1Q }; ERROR: Source and destination horizontal stride must equal and a multiple of a qword when the execution type is 64-bit mov(8) g4<1>D g12<8,4,2>UD { align1 1Q }; mov(8) g7<1>DF -g7<4,4,1>D { align1 1Q }; ERROR: Source and destination horizontal stride must equal and a multiple of a qword when the execution type is 64-bit mov(8) g11<1>DF -g2<4,4,1>D { align1 1Q }; ERROR: Source and destination horizontal stride must equal and a multiple of a qword when the execution type is 64-bit mov(8) g13<1>DF -g4<4,4,1>D { align1 1Q }; ERROR: Source and destination horizontal stride must equal and a multiple of a qword when the execution type is 64-bit cmp.nz.f0(8) g7<1>DF g7<4,4,1>DF g3.1<0,1,0>DF { align1 1Q }; cmp.nz.f0(8) g4<1>DF g5<4,4,1>DF g3<0,1,0>DF { align1 1Q }; mov(8) g2<1>D g7<8,4,2>UD { align1 1Q }; cmp.nz.f0(8) g6<1>DF g11<4,4,1>DF g3.2<0,1,0>DF { align1 1Q }; mov(8) g4<1>D g4<8,4,2>UD { align1 1Q }; cmp.nz.f0(8) g8<1>DF g13<4,4,1>DF g3.3<0,1,0>DF { align1 1Q }; mov(8) g3<1>D g6<8,4,2>UD { align1 1Q }; or(8) g2<1>UD g4<8,8,1>UD g2<8,8,1>UD { align1 1Q compacted }; mov(8) g4<1>D g8<8,4,2>UD { align1 1Q }; or(8) g2<1>UD g2<8,8,1>UD g3<8,8,1>UD { align1 1Q compacted }; or(8) g2<1>UD g2<8,8,1>UD g4<8,8,1>UD { align1 1Q compacted }; mov(8) g124<1>F -g2<8,8,1>D { align1 1Q compacted }; not(8) g4<1>D g2<8,8,1>D { align1 1Q compacted }; mov(8) g125<1>F -g4<8,8,1>D { align1 1Q compacted }; send(8) null<1>F g119<8,8,1>F urb 1 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; END B0
Patch sent to the mailing list: https://patchwork.freedesktop.org/patch/255965/
Should be fixed with the following commit. Feel free to reopen otherwise. commit 497675c21ee34dfe1e8f9dfe62f6a3011f8062e5 Author: Jason Ekstrand <jason.ekstrand@intel.com> Date: Wed Oct 10 15:17:11 2018 -0700 intel/fs: Fix nir_op_b2[fi] with 64-bit result on Gen8 LP and Gen9 LP
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