| Summary: | [bisected][regression] vk cts fp16 arithmetic failures | ||
|---|---|---|---|
| Product: | Mesa | Reporter: | Clayton Craft <clayton.a.craft> |
| Component: | Drivers/DRI/i965 | Assignee: | Ian Romanick <idr> |
| Status: | RESOLVED FIXED | QA Contact: | Intel 3D Bugs Mailing List <intel-3d-bugs> |
| Severity: | normal | ||
| Priority: | medium | Keywords: | bisected, regression |
| Version: | git | ||
| Hardware: | Other | ||
| OS: | All | ||
| Whiteboard: | |||
| i915 platform: | i915 features: | ||
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Description
Clayton Craft
2019-04-19 22:46:54 UTC
I'm planning to land https://gitlab.freedesktop.org/mesa/mesa/merge_requests/694 in a little bit. Fixed by: commit a6ccc4c0c893cfd978068f1d75ad0e001182b381 Author: Ian Romanick <ian.d.romanick@intel.com> Date: Thu Apr 18 15:09:06 2019 -0700 intel/fs: Add support for float16 to the fsign optimizations Commit ad98fbc2174 ("intel/fs: Refactor code generation for nir_op_fsign to its own function") criss-crossed with c2b8fb9a810 ("anv/device: expose VK_KHR_shader_float16_int8 in gen8+"), and I was not paying enough attention when I rebased. This adds back the float16 changes and enables the optimization. v2: Incorporate more changes from 19cd2f5debd and a8d8b1a1391 that I missed in the previous version. Fixes: ad98fbc2174 ("intel/fs: Refactor code generation for nir_op_fsign to its own function") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110474 Reviewed-by: Matt Turner <mattst88@gmail.com> [v1] |
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