Bug 109056

Summary: Image load store regressions
Product: Mesa Reporter: Mark Janes <mark.a.janes>
Component: Drivers/DRI/i965Assignee: Eric Anholt <eric>
Status: RESOLVED FIXED QA Contact: Intel 3D Bugs Mailing List <intel-3d-bugs>
Severity: normal    
Priority: medium Keywords: bisected, regression
Version: unspecified   
Hardware: Other   
OS: All   
Whiteboard:
i915 platform: i915 features:

Description Mark Janes 2018-12-13 18:16:33 UTC
Vulkan tests regresson on i965:

dEQP-VK.image.texel_view_compatible.compute.basic.image_store.bc1_rgb_srgb_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.basic.image_store.bc1_rgb_unorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.basic.image_store.bc1_rgba_srgb_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.basic.image_store.bc1_rgba_unorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.basic.image_store.bc4_snorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.basic.image_store.bc4_unorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.extended.image_store.bc1_rgb_srgb_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.extended.image_store.bc1_rgb_unorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.extended.image_store.bc1_rgba_srgb_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.extended.image_store.bc1_rgba_unorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.extended.image_store.bc4_snorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.extended.image_store.bc4_unorm_block.r16g16b16a16_sfloat

In the output for these tests:
error: src->ssa->num_components == num_components (../src/compiler/nir/nir_validate.c:206)

Bisected to:
06fbcd2cd5cc5702c9039c26d20082a99bc157bf
Author:     Eric Anholt <eric@anholt.net>

intel: Simplify the half-float packing in image load/store lowering.

This was noted by Jason in review when I tried to make a helper for the
old path.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Comment 1 Mark Janes 2018-12-13 18:20:39 UTC
Also regressed by 06fbcd2cd5cc5702c9039c26d20082a99bc157bf:

piglit.spec.arb_shader_image_load_store.qualifiers
piglit.spec.arb_shader_image_load_store.invalid


Separately, KHR-GL46.shader_image_load_store.multiple-uniforms was regressed by another patch in the series:

Invalid result! Image format: rgb10_a2ui Original value: 0x40104208 Copied value: 0x401041ff Negated value: 0x5ff7fdff

d3e046e76c06978d92bc7311bf02926e888159dc
Author:     Eric Anholt <eric@anholt.net>

nir: Pull some of intel's image load/store format conversion to nir_format.h

I needed the same functions for v3d.  Note that the color value in the
Intel lowering has already been cut down to image.chans num_components.

v2: Drop the half float one, since it was a 1-liner after cleanup.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Comment 2 Lionel Landwerlin 2018-12-13 18:30:07 UTC
You'll need the CTS :

commit cfb8d04724da69306602c91c077eebf0af03719c (HEAD)
Merge: a3e64b16f 39bc6c57a
Author: Alexander Galazin <alexander.galazin@arm.com>
Date:   Thu Aug 2 10:27:48 2018 +0200

    Merge vk-gl-cts/vulkan-cts-1.1.0 into vk-gl-cts/vulkan-cts-1.1.1

Because those particular tests (bc* -> sfloat) kind of disappeared on more recent versions.

Also seems to affect only BDW so stub your driver to the right platform!
Comment 3 Mark Janes 2018-12-13 18:50:12 UTC
(In reply to Lionel Landwerlin from comment #2)
> Also seems to affect only BDW so stub your driver to the right platform!

I should have specified that BDW and HSW regressed for the vulkan tests.
Comment 4 Lionel Landwerlin 2018-12-13 22:15:00 UTC
The actual commit introducing this issue is : 

commit 06fbcd2cd5cc5702c9039c26d20082a99bc157bf
Author: Eric Anholt <eric@anholt.net>
Date:   Wed Dec 12 11:29:29 2018 -0800

    intel: Simplify the half-float packing in image load/store lowering.

But I can't really understand how this is correct because it reduces the number of channels. Do we need to stuff the other channels with 0s?
Comment 5 Mark Janes 2018-12-13 23:05:30 UTC
(In reply to Lionel Landwerlin from comment #4)
> But I can't really understand how this is correct because it reduces the
> number of channels. Do we need to stuff the other channels with 0s?

Eric reverted the commit, fixing the vulkan tests.
Comment 6 Mark Janes 2018-12-13 23:47:36 UTC
With Eric's recent series, the piglit and vulkan regressions are fixed.

The only remaining regression is:
KHR-GL46.shader_image_load_store.multiple-uniforms

Sample failure here:
https://mesa-ci.01.org/mesa_master/builds/14758/results/521013591

The remaining regression was initially bisected to:
d3e046e76c06978d92bc7311bf02926e888159dc
nir: Pull some of intel's image load/store format conversion to nir_format.h
Comment 7 Mark Janes 2019-02-20 18:14:03 UTC
The last regression documented by this bug was fixed with:

708d8f4d0a557f509435e05696a4096a2900d748
Author:     Eric Anholt <eric@anholt.net>
Commit:     Jason Ekstrand <jason@jlekstrand.net>

nir: Fix clamping of uints for image store lowering.

I botched some copy-and-paste and clamped to signed int max instead of
uint max.  Fixes KHR-GL46.shader_image_load_store.multiple-uniforms on
skl.

Fixes: d3e046e76c06 ("nir: Pull some of intel's image load/store format
conversion to nir_format.h")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

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