Bug 103115

Summary: [BSW BXT GLK] dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_int64
Product: Mesa Reporter: Mark Janes <mark.a.janes>
Component: Drivers/DRI/i965Assignee: Matt Turner <mattst88>
Status: RESOLVED FIXED QA Contact: Intel 3D Bugs Mailing List <intel-3d-bugs>
Severity: normal    
Priority: medium    
Version: git   
Hardware: Other   
OS: All   
Whiteboard:
i915 platform: i915 features:
Bug Depends on:    
Bug Blocks: 103491    

Description Mark Janes 2017-10-05 19:57:06 UTC 
This test and three others regressed at 
mesa 2572c2771d0cab0b9bc489d354ede44dfc88547b
Author:     Matt Turner <mattst88@gmail.com>
i965: Validate "Special Requirements for Handling Double Precision Data Types"

I did not implement:

   CNL's restriction on 64-bit int + align16, because I don't think
   we'll ever use this combination regardless of hardware generation.

   The restriction on immediate DF -> F conversions, because there's no
   reason to ever generate that, and I don't even know how DF -> F
   conversions are supposed to work in Align16 since (1) the dst stride
   must be 1, but (2) the dst stride would have to be 2 for src and dst
   strides to be aligned.

---------------------------------------------
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_int64
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_uint64
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_uint64
+dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64

deqp-vk: /home/jenkins/workspace/Leeroy_2/repos/mesa/src/intel/compiler/brw_fs_generator.cpp:2203: int fs_generator::generate_code(const cfg_t*, int): Assertion `validated' failed.
Comment 1 Matt Turner 2017-11-08 23:21:39 UTC 
Testing a fix.
Comment 2 Matt Turner 2017-11-09 21:42:52 UTC 
Patch on the list to fix this:

i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK

Also fixes

KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot
Comment 3 Matt Turner 2017-11-14 18:57:14 UTC 
commit cfcfa0b9cd1b1d563a988b1250950057c4612ac9
Author: Matt Turner <mattst88@gmail.com>
Date:   Wed Nov 8 15:14:19 2017 -0800

    i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK

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