From a71b604417bc544ec87683815c33e77236d5beaa Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 21 Feb 2013 18:49:06 -0500 Subject: [PATCH 2/4] r600g: set additional cp_coher_cntl bits for 6xx/7xx flush I don't see why we shouldn't be setting these bits on 6xx/7xx as well. They shouldn't hurt anything and we may be missing synchronizations with certain blocks by not setting them. The ddx already sets cp_coher_cntl in a similar manner. Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher --- src/gallium/drivers/r600/r600_hw_context.c | 15 +++++++++++++-- 1 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index 395347e..62a88c1 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -670,10 +670,21 @@ void r600_flush_emit(struct r600_context *rctx) S_0085F0_SMX_ACTION_ENA(1) | S_0085F0_FULL_CACHE_ENA(1); } else { - cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) | - S_0085F0_SH_ACTION_ENA(1) | + cp_coher_cntl = S_0085F0_CB0_DEST_BASE_ENA(1) | + S_0085F0_CB1_DEST_BASE_ENA(1) | + S_0085F0_CB2_DEST_BASE_ENA(1) | + S_0085F0_CB3_DEST_BASE_ENA(1) | + S_0085F0_CB4_DEST_BASE_ENA(1) | + S_0085F0_CB5_DEST_BASE_ENA(1) | + S_0085F0_CB6_DEST_BASE_ENA(1) | + S_0085F0_CB7_DEST_BASE_ENA(1) | + S_0085F0_DB_DEST_BASE_ENA(1) | S_0085F0_VC_ACTION_ENA(1) | S_0085F0_TC_ACTION_ENA(1) | + S_0085F0_CB_ACTION_ENA(1) | + S_0085F0_DB_ACTION_ENA(1) | + S_0085F0_SH_ACTION_ENA(1) | + S_0085F0_SMX_ACTION_ENA(1) | S_0085F0_FULL_CACHE_ENA(1); } } -- 1.7.7.5