From 70c396086bcf3635e967f33e6b1603cde79594b5 Mon Sep 17 00:00:00 2001
From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri, 21 Dec 2012 08:58:43 +0000
Subject: [PATCH] uxa: Remove support for relaxed fencing

From the looks of https://bugzilla.redhat.com/show_bug.cgi?id=877461 it
seems that we have an issue calculating the required surface sizes
leading to a single EU dieing waiting upon the sampler. Let's enable the
pot-fence size pessimism for all generations...

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 src/intel.h        |    1 -
 src/intel_driver.c |   12 ------------
 src/intel_memory.c |   23 +++++++++--------------
 src/intel_uxa.c    |    2 +-
 4 files changed, 10 insertions(+), 28 deletions(-)

diff --git a/src/intel.h b/src/intel.h
index 53ce33c..cd74593 100644
--- a/src/intel.h
+++ b/src/intel.h
@@ -209,7 +209,6 @@ typedef struct intel_screen_private {
 #define INTEL_TILING_ALL (~0)
 
 	Bool swapbuffers_wait;
-	Bool has_relaxed_fencing;
 
 	int Chipset;
 	EntityInfoPtr pEnt;
diff --git a/src/intel_driver.c b/src/intel_driver.c
index 5d3e103..b14f3cf 100644
--- a/src/intel_driver.c
+++ b/src/intel_driver.c
@@ -585,18 +585,6 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags)
 
 	intel->has_prime_vmap_flush = has_prime_vmap_flush(intel);
 
-	intel->has_relaxed_fencing =
-		xf86ReturnOptValBool(intel->Options,
-				     OPTION_RELAXED_FENCING,
-				     INTEL_INFO(intel)->gen >= 033);
-	/* And override the user if there is no kernel support */
-	if (intel->has_relaxed_fencing)
-		intel->has_relaxed_fencing = has_relaxed_fencing(intel);
-
-	xf86DrvMsg(scrn->scrnIndex, X_CONFIG,
-		   "Relaxed fencing %s\n",
-		   intel->has_relaxed_fencing ? "enabled" : "disabled");
-
 	/* SwapBuffers delays to avoid tearing */
 	intel->swapbuffers_wait = xf86ReturnOptValBool(intel->Options,
 						       OPTION_SWAPBUFFERS_WAIT,
diff --git a/src/intel_memory.c b/src/intel_memory.c
index e51fa33..0bdadcf 100644
--- a/src/intel_memory.c
+++ b/src/intel_memory.c
@@ -94,22 +94,17 @@ unsigned long intel_get_fence_size(intel_screen_private *intel, unsigned long si
 	unsigned long i;
 	unsigned long start;
 
-	if (INTEL_INFO(intel)->gen >= 040 || intel->has_relaxed_fencing) {
-		/* The 965 can have fences at any page boundary. */
-		return ALIGN(size, 4096);
-	} else {
-		/* Align the size to a power of two greater than the smallest fence
-		 * size.
-		 */
-		if (IS_GEN3(intel))
-			start = MB(1);
-		else
-			start = KB(512);
+	/* Align the size to a power of two greater than the smallest fence
+	 * size.
+	 */
+	if (IS_GEN3(intel))
+		start = MB(1);
+	else
+		start = KB(512);
 
-		for (i = start; i < size; i <<= 1) ;
+	for (i = start; i < size; i <<= 1) ;
 
-		return i;
-	}
+	return i;
 }
 
 /**
diff --git a/src/intel_uxa.c b/src/intel_uxa.c
index f5ac0a6..c18191c 100644
--- a/src/intel_uxa.c
+++ b/src/intel_uxa.c
@@ -185,7 +185,7 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap,
 			 * aligned with a minimum of 1 MiB, so causes
 			 * massive overallocation for small textures.
 			 */
-			if (size < 1024*1024/2 && !intel->has_relaxed_fencing)
+			if (size < 1024*1024/2)
 				*tiling = I915_TILING_NONE;
 		} else if (!(usage & INTEL_CREATE_PIXMAP_DRI2) && size <= 4096) {
 			/* Disable tiling beneath a page size, we will not see
-- 
1.7.10.4