[ 0.000000] Initializing cgroup subsys cpuset [ 0.000000] Initializing cgroup subsys cpu [ 0.000000] Linux version 2.6.33-020633-generic (root@zinc) (gcc version 4.2.3 (Ubuntu 4.2.3-2ubuntu7)) #020633 SMP Thu Feb 25 10:10:03 UTC 2010 [ 0.000000] Command line: BOOT_IMAGE=/vmlinuz-2.6.33-020633-generic root=UUID=d2722cbe-935c-4d0a-a257-de3c10820137 ro quiet splash i915.modeset=1 drm.debug=0x04 video=640x480 [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: 0000000000000000 - 000000000009f000 (usable) [ 0.000000] BIOS-e820: 000000000009f000 - 00000000000a0000 (reserved) [ 0.000000] BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved) [ 0.000000] BIOS-e820: 0000000000100000 - 000000007f7f0000 (usable) [ 0.000000] BIOS-e820: 000000007f7f0000 - 000000007f7f3000 (ACPI NVS) [ 0.000000] BIOS-e820: 000000007f7f3000 - 000000007f800000 (ACPI data) [ 0.000000] BIOS-e820: 00000000e0000000 - 00000000f0000000 (reserved) [ 0.000000] BIOS-e820: 00000000fec00000 - 0000000100000000 (reserved) [ 0.000000] NX (Execute Disable) protection: active [ 0.000000] DMI 2.2 present. [ 0.000000] Phoenix BIOS detected: BIOS may corrupt low RAM, working around it. [ 0.000000] e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved) [ 0.000000] No AGP bridge found [ 0.000000] last_pfn = 0x7f7f0 max_arch_pfn = 0x400000000 [ 0.000000] MTRR default type: uncachable [ 0.000000] MTRR fixed ranges enabled: [ 0.000000] 00000-9FFFF write-back [ 0.000000] A0000-BFFFF uncachable [ 0.000000] C0000-C9FFF write-protect [ 0.000000] CA000-EFFFF uncachable [ 0.000000] F0000-FFFFF write-through [ 0.000000] MTRR variable ranges enabled: [ 0.000000] 0 base 000000000 mask F80000000 write-back [ 0.000000] 1 base 07F800000 mask FFF800000 uncachable [ 0.000000] 2 disabled [ 0.000000] 3 disabled [ 0.000000] 4 disabled [ 0.000000] 5 disabled [ 0.000000] 6 disabled [ 0.000000] 7 disabled [ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 [ 0.000000] Scanning 0 areas for low memory corruption [ 0.000000] modified physical RAM map: [ 0.000000] modified: 0000000000000000 - 0000000000010000 (reserved) [ 0.000000] modified: 0000000000010000 - 000000000009f000 (usable) [ 0.000000] modified: 000000000009f000 - 00000000000a0000 (reserved) [ 0.000000] modified: 00000000000f0000 - 0000000000100000 (reserved) [ 0.000000] modified: 0000000000100000 - 000000007f7f0000 (usable) [ 0.000000] modified: 000000007f7f0000 - 000000007f7f3000 (ACPI NVS) [ 0.000000] modified: 000000007f7f3000 - 000000007f800000 (ACPI data) [ 0.000000] modified: 00000000e0000000 - 00000000f0000000 (reserved) [ 0.000000] modified: 00000000fec00000 - 0000000100000000 (reserved) [ 0.000000] initial memory mapped : 0 - 20000000 [ 0.000000] found SMP MP-table at [ffff8800000f38b0] f38b0 [ 0.000000] init_memory_mapping: 0000000000000000-000000007f7f0000 [ 0.000000] 0000000000 - 007f600000 page 2M [ 0.000000] 007f600000 - 007f7f0000 page 4k [ 0.000000] kernel direct mapping tables up to 7f7f0000 @ 16000-1a000 [ 0.000000] RAMDISK: 377ec000 - 37fef0f5 [ 0.000000] ACPI: RSDP 00000000000f7980 00014 (v00 FIC ) [ 0.000000] ACPI: RSDT 000000007f7f3040 00030 (v01 FIC P4M915G 42302E31 AWRD 00000000) [ 0.000000] ACPI: FACP 000000007f7f30c0 00074 (v01 FIC P4M915G 42302E31 AWRD 00000000) [ 0.000000] ACPI: DSDT 000000007f7f3180 043D8 (v01 INTELR AWRDACPI 00001000 MSFT 0100000E) [ 0.000000] ACPI: FACS 000000007f7f0000 00040 [ 0.000000] ACPI: MCFG 000000007f7f76c0 0003C (v01 FIC P4M915G 42302E31 AWRD 00000000) [ 0.000000] ACPI: APIC 000000007f7f75c0 00084 (v01 FIC P4M915G 42302E31 AWRD 00000000) [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] No NUMA configuration found [ 0.000000] Faking a node at 0000000000000000-000000007f7f0000 [ 0.000000] Bootmem setup node 0 0000000000000000-000000007f7f0000 [ 0.000000] NODE_DATA [0000000000018000 - 000000000001cfff] [ 0.000000] bootmap [000000000001d000 - 000000000002ceff] pages 10 [ 0.000000] (12 early reservations) ==> bootmem [0000000000 - 007f7f0000] [ 0.000000] #0 [0000000000 - 0000001000] BIOS data page ==> [0000000000 - 0000001000] [ 0.000000] #1 [0001000000 - 0001c92ff4] TEXT DATA BSS ==> [0001000000 - 0001c92ff4] [ 0.000000] #2 [00377ec000 - 0037fef0f5] RAMDISK ==> [00377ec000 - 0037fef0f5] [ 0.000000] #3 [0001c93000 - 0001c930d6] BRK ==> [0001c93000 - 0001c930d6] [ 0.000000] #4 [00000f38c0 - 0000100000] BIOS reserved ==> [00000f38c0 - 0000100000] [ 0.000000] #5 [00000f38b0 - 00000f38c0] MP-table mpf ==> [00000f38b0 - 00000f38c0] [ 0.000000] #6 [000009f000 - 00000f1e14] BIOS reserved ==> [000009f000 - 00000f1e14] [ 0.000000] #7 [00000f1f3c - 00000f38b0] BIOS reserved ==> [00000f1f3c - 00000f38b0] [ 0.000000] #8 [00000f1e14 - 00000f1f3c] MP-table mpc ==> [00000f1e14 - 00000f1f3c] [ 0.000000] #9 [0000010000 - 0000012000] TRAMPOLINE ==> [0000010000 - 0000012000] [ 0.000000] #10 [0000012000 - 0000016000] ACPI WAKEUP ==> [0000012000 - 0000016000] [ 0.000000] #11 [0000016000 - 0000018000] PGTABLE ==> [0000016000 - 0000018000] [ 0.000000] [ffffea0000000000-ffffea0001bfffff] PMD -> [ffff880002200000-ffff880003dfffff] on node 0 [ 0.000000] Zone PFN ranges: [ 0.000000] DMA 0x00000010 -> 0x00001000 [ 0.000000] DMA32 0x00001000 -> 0x00100000 [ 0.000000] Normal 0x00100000 -> 0x00100000 [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[2] active PFN ranges [ 0.000000] 0: 0x00000010 -> 0x0000009f [ 0.000000] 0: 0x00000100 -> 0x0007f7f0 [ 0.000000] On node 0 totalpages: 522111 [ 0.000000] DMA zone: 56 pages used for memmap [ 0.000000] DMA zone: 104 pages reserved [ 0.000000] DMA zone: 3823 pages, LIFO batch:0 [ 0.000000] DMA32 zone: 7084 pages used for memmap [ 0.000000] DMA32 zone: 511044 pages, LIFO batch:31 [ 0.000000] ACPI: PM-Timer IO Port: 0x408 [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] disabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x03] disabled) [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1]) [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1]) [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1]) [ 0.000000] ACPI: IOAPIC (id[0x04] address[0xfec00000] gsi_base[0]) [ 0.000000] IOAPIC[0]: apic_id 4, version 32, address 0xfec00000, GSI 0-23 [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) [ 0.000000] ACPI: IRQ0 used by override. [ 0.000000] ACPI: IRQ2 used by override. [ 0.000000] ACPI: IRQ9 used by override. [ 0.000000] Using ACPI (MADT) for SMP configuration information [ 0.000000] SMP: Allowing 4 CPUs, 2 hotplug CPUs [ 0.000000] nr_irqs_gsi: 24 [ 0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000 [ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000f0000 [ 0.000000] PM: Registered nosave memory: 00000000000f0000 - 0000000000100000 [ 0.000000] Allocating PCI resources starting at 7f800000 (gap: 7f800000:60800000) [ 0.000000] Booting paravirtualized kernel on bare hardware [ 0.000000] setup_percpu: NR_CPUS:64 nr_cpumask_bits:64 nr_cpu_ids:4 nr_node_ids:1 [ 0.000000] PERCPU: Embedded 30 pages/cpu @ffff880001e00000 s91544 r8192 d23144 u524288 [ 0.000000] pcpu-alloc: s91544 r8192 d23144 u524288 alloc=1*2097152 [ 0.000000] pcpu-alloc: [0] 0 1 2 3 [ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 514867 [ 0.000000] Policy zone: DMA32 [ 0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz-2.6.33-020633-generic root=UUID=d2722cbe-935c-4d0a-a257-de3c10820137 ro quiet splash i915.modeset=1 drm.debug=0x04 video=640x480 [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) [ 0.000000] Checking aperture... [ 0.000000] No AGP bridge found [ 0.000000] Calgary: detecting Calgary via BIOS EBDA area [ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing! [ 0.000000] Memory: 2038032k/2088896k available (5408k kernel code, 452k absent, 50412k reserved, 5594k data, 736k init) [ 0.000000] SLUB: Genslabs=14, HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 [ 0.000000] Hierarchical RCU implementation. [ 0.000000] NR_IRQS:4352 nr_irqs:440 [ 0.000000] Console: colour VGA+ 80x25 [ 0.000000] console [tty0] enabled [ 0.000000] allocated 20971520 bytes of page_cgroup [ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups [ 0.000000] Fast TSC calibration using PIT [ 0.000000] Detected 2793.151 MHz processor. [ 0.020009] Calibrating delay loop (skipped), value calculated using timer frequency.. 5586.30 BogoMIPS (lpj=27931510) [ 0.020044] Security Framework initialized [ 0.020052] SELinux: Disabled at boot. [ 0.020370] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes) [ 0.021593] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes) [ 0.022170] Mount-cache hash table entries: 256 [ 0.022377] Initializing cgroup subsys ns [ 0.022383] Initializing cgroup subsys cpuacct [ 0.022389] Initializing cgroup subsys memory [ 0.022400] Initializing cgroup subsys devices [ 0.022404] Initializing cgroup subsys freezer [ 0.022407] Initializing cgroup subsys net_cls [ 0.022442] CPU: Physical Processor ID: 0 [ 0.022445] CPU: Processor Core ID: 0 [ 0.022449] mce: CPU supports 4 MCE banks [ 0.022464] CPU0: Thermal monitoring enabled (TM1) [ 0.022471] using mwait in idle threads. [ 0.022474] Performance Events: no PMU driver, software events only. [ 0.031109] ACPI: Core revision 20091214 [ 0.040081] Setting APIC routing to flat [ 0.040407] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 [ 0.145300] CPU0: Intel(R) Pentium(R) 4 CPU 2.80GHz stepping 09 [ 0.150000] Booting Node 0, Processors #1 [ 0.310036] Brought up 2 CPUs [ 0.310044] Total of 2 processors activated (11172.43 BogoMIPS). [ 0.310563] regulator: core version 0.5 [ 0.310563] Time: 21:57:16 Date: 03/12/10 [ 0.310563] NET: Registered protocol family 16 [ 0.310691] ACPI: bus type pci registered [ 0.310789] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) [ 0.310797] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820 [ 0.314456] PCI: Using configuration type 1 for base access [ 0.315616] bio: create slab at 0 [ 0.315616] ACPI: EC: Look up EC in DSDT [ 0.326882] ACPI: Interpreter enabled [ 0.326889] ACPI: (supports S0 S3 S4 S5) [ 0.326929] ACPI: Using IOAPIC for interrupt routing [ 0.333919] ACPI: No dock devices found. [ 0.334069] ACPI: PCI Root Bridge [PCI0] (0000:00) [ 0.334113] pci_root PNP0A08:00: ignoring host bridge windows from ACPI; boot with "pci=use_crs" to use them [ 0.334359] pci_root PNP0A08:00: host bridge window [io 0x0000-0x0cf7] (ignored) [ 0.334364] pci_root PNP0A08:00: host bridge window [io 0x0d00-0xffff] (ignored) [ 0.334367] pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff] (ignored) [ 0.334371] pci_root PNP0A08:00: host bridge window [mem 0x000c0000-0x000dffff] (ignored) [ 0.334374] pci_root PNP0A08:00: host bridge window [mem 0x7f800000-0xfebfffff] (ignored) [ 0.334451] pci 0000:00:02.0: reg 10: [mem 0xfdf00000-0xfdf7ffff] [ 0.334458] pci 0000:00:02.0: reg 14: [io 0xff00-0xff07] [ 0.334464] pci 0000:00:02.0: reg 18: [mem 0xd0000000-0xdfffffff pref] [ 0.334470] pci 0000:00:02.0: reg 1c: [mem 0xfdf80000-0xfdfbffff] [ 0.334510] pci 0000:00:02.1: reg 10: [mem 0xfde80000-0xfdefffff] [ 0.334607] pci 0000:00:1b.0: reg 10: [mem 0xfdff8000-0xfdffbfff 64bit] [ 0.334656] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold [ 0.334661] pci 0000:00:1b.0: PME# disabled [ 0.334712] pci 0000:00:1d.0: reg 20: [io 0xfe00-0xfe1f] [ 0.334768] pci 0000:00:1d.1: reg 20: [io 0xfd00-0xfd1f] [ 0.334823] pci 0000:00:1d.2: reg 20: [io 0xfc00-0xfc1f] [ 0.334877] pci 0000:00:1d.3: reg 20: [io 0xfb00-0xfb1f] [ 0.334926] pci 0000:00:1d.7: reg 10: [mem 0xfdfff000-0xfdfff3ff] [ 0.334978] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold [ 0.334984] pci 0000:00:1d.7: PME# disabled [ 0.335106] pci 0000:00:1f.0: Force enabled HPET at 0xfed00000 [ 0.335115] pci 0000:00:1f.0: quirk: [io 0x0400-0x047f] claimed by ICH6 ACPI/GPIO/TCO [ 0.335121] pci 0000:00:1f.0: quirk: [io 0x0480-0x04bf] claimed by ICH6 GPIO [ 0.335126] pci 0000:00:1f.0: LPC Generic IO decode 1 PIO at 0800-087f [ 0.335130] pci 0000:00:1f.0: LPC Generic IO decode 2 PIO at 0290-029f [ 0.335158] pci 0000:00:1f.1: reg 10: [io 0x0000-0x0007] [ 0.335166] pci 0000:00:1f.1: reg 14: [io 0x0000-0x0003] [ 0.335173] pci 0000:00:1f.1: reg 18: [io 0x0000-0x0007] [ 0.335181] pci 0000:00:1f.1: reg 1c: [io 0x0000-0x0003] [ 0.335188] pci 0000:00:1f.1: reg 20: [io 0xfa00-0xfa0f] [ 0.335232] pci 0000:00:1f.2: reg 10: [io 0xf900-0xf907] [ 0.335239] pci 0000:00:1f.2: reg 14: [io 0xf800-0xf803] [ 0.335245] pci 0000:00:1f.2: reg 18: [io 0xf700-0xf707] [ 0.335252] pci 0000:00:1f.2: reg 1c: [io 0xf600-0xf603] [ 0.335259] pci 0000:00:1f.2: reg 20: [io 0xf500-0xf50f] [ 0.335287] pci 0000:00:1f.2: PME# supported from D3hot [ 0.335291] pci 0000:00:1f.2: PME# disabled [ 0.335340] pci 0000:00:1f.3: reg 20: [io 0x0500-0x051f] [ 0.335419] pci 0000:01:05.0: reg 10: [mem 0xfddff000-0xfddff7ff] [ 0.335428] pci 0000:01:05.0: reg 14: [io 0xef00-0xef7f] [ 0.335478] pci 0000:01:05.0: supports D2 [ 0.335481] pci 0000:01:05.0: PME# supported from D2 D3hot D3cold [ 0.335486] pci 0000:01:05.0: PME# disabled [ 0.335521] pci 0000:01:06.0: reg 10: [io 0xec00-0xecff] [ 0.335529] pci 0000:01:06.0: reg 14: [mem 0xfddfe000-0xfddfe0ff] [ 0.335559] pci 0000:01:06.0: reg 30: [mem 0x00000000-0x0000ffff pref] [ 0.335581] pci 0000:01:06.0: supports D1 D2 [ 0.335584] pci 0000:01:06.0: PME# supported from D1 D2 D3hot D3cold [ 0.335589] pci 0000:01:06.0: PME# disabled [ 0.335637] pci 0000:00:1e.0: PCI bridge to [bus 01-01] (subtractive decode) [ 0.335642] pci 0000:00:1e.0: bridge window [io 0xe000-0xefff] [ 0.335647] pci 0000:00:1e.0: bridge window [mem 0xfdd00000-0xfddfffff] [ 0.335655] pci 0000:00:1e.0: bridge window [mem 0xfdc00000-0xfdcfffff 64bit pref] [ 0.335669] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] [ 0.335865] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.HUB0._PRT] [ 0.351973] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 7 9 *10 11 12 14 15) [ 0.352128] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 7 9 10 11 *12 14 15) [ 0.352280] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 7 9 10 *11 12 14 15) [ 0.352436] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 7 9 10 11 12 14 *15) [ 0.352584] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 7 9 10 11 12 14 15) *0, disabled. [ 0.352733] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 7 9 10 11 12 14 15) *0, disabled. [ 0.352884] ACPI: PCI Interrupt Link [LNK0] (IRQs 3 4 5 7 9 10 11 12 14 15) *0, disabled. [ 0.353037] ACPI: PCI Interrupt Link [LNK1] (IRQs 3 4 *5 7 9 10 11 12 14 15) [ 0.353175] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none [ 0.353192] vgaarb: loaded [ 0.353354] SCSI subsystem initialized [ 0.353416] libata version 3.00 loaded. [ 0.353416] usbcore: registered new interface driver usbfs [ 0.353416] usbcore: registered new interface driver hub [ 0.353416] usbcore: registered new device driver usb [ 0.353416] ACPI: WMI: Mapper loaded [ 0.353416] PCI: Using ACPI for IRQ routing [ 0.353416] PCI: pci_cache_line_size set to 64 bytes [ 0.353416] Bluetooth: Core ver 2.15 [ 0.353416] NET: Registered protocol family 31 [ 0.353416] Bluetooth: HCI device and connection manager initialized [ 0.353416] Bluetooth: HCI socket layer initialized [ 0.353416] NetLabel: Initializing [ 0.353416] NetLabel: domain hash size = 128 [ 0.353416] NetLabel: protocols = UNLABELED CIPSOv4 [ 0.353416] NetLabel: unlabeled traffic allowed by default [ 0.353416] hpet clockevent registered [ 0.353416] HPET: 3 timers in total, 0 timers will be used for per-cpu timer [ 0.353416] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0 [ 0.353416] hpet0: 3 comparators, 64-bit 14.318180 MHz counter [ 0.360024] Switching to clocksource tsc [ 0.362572] pnp: PnP ACPI init [ 0.362598] ACPI: bus type pnp registered [ 0.366173] pnp: PnP ACPI: found 11 devices [ 0.366177] ACPI: ACPI bus type pnp unregistered [ 0.366194] system 00:01: [io 0x04d0-0x04d1] has been reserved [ 0.366198] system 00:01: [io 0x0290-0x029f] has been reserved [ 0.366202] system 00:01: [io 0x0800-0x0805] has been reserved [ 0.366206] system 00:01: [io 0x0880-0x088f] has been reserved [ 0.366217] system 00:07: [io 0x0400-0x04bf] could not be reserved [ 0.366226] system 00:09: [mem 0xe0000000-0xefffffff] has been reserved [ 0.366235] system 00:0a: [mem 0x000cc000-0x000cffff] has been reserved [ 0.366239] system 00:0a: [mem 0x000f0000-0x000f7fff] could not be reserved [ 0.366243] system 00:0a: [mem 0x000f8000-0x000fbfff] could not be reserved [ 0.366246] system 00:0a: [mem 0x000fc000-0x000fffff] could not be reserved [ 0.366250] system 00:0a: [mem 0x7f7f0000-0x7f7fffff] could not be reserved [ 0.366254] system 00:0a: [mem 0x00000000-0x0009ffff] could not be reserved [ 0.366258] system 00:0a: [mem 0x00100000-0x7f7effff] could not be reserved [ 0.366262] system 00:0a: [mem 0xfec00000-0xfec00fff] could not be reserved [ 0.366266] system 00:0a: [mem 0xfed13000-0xfed1dfff] has been reserved [ 0.366271] system 00:0a: [mem 0xfed20000-0xfed8ffff] has been reserved [ 0.366275] system 00:0a: [mem 0xfee00000-0xfee00fff] has been reserved [ 0.366279] system 00:0a: [mem 0xffb00000-0xffb7ffff] has been reserved [ 0.366282] system 00:0a: [mem 0xfff00000-0xffffffff] has been reserved [ 0.366286] system 00:0a: [mem 0x000e0000-0x000effff] has been reserved [ 0.371056] pci 0000:01:06.0: BAR 6: assigned [mem 0xfdc00000-0xfdc0ffff pref] [ 0.371061] pci 0000:00:1e.0: PCI bridge to [bus 01-01] [ 0.371065] pci 0000:00:1e.0: bridge window [io 0xe000-0xefff] [ 0.371071] pci 0000:00:1e.0: bridge window [mem 0xfdd00000-0xfddfffff] [ 0.371077] pci 0000:00:1e.0: bridge window [mem 0xfdc00000-0xfdcfffff 64bit pref] [ 0.371092] pci 0000:00:1e.0: setting latency timer to 64 [ 0.371097] pci_bus 0000:00: resource 0 [io 0x0000-0xffff] [ 0.371100] pci_bus 0000:00: resource 1 [mem 0x00000000-0xffffffffffffffff] [ 0.371105] pci_bus 0000:01: resource 0 [io 0xe000-0xefff] [ 0.371109] pci_bus 0000:01: resource 1 [mem 0xfdd00000-0xfddfffff] [ 0.371112] pci_bus 0000:01: resource 2 [mem 0xfdc00000-0xfdcfffff 64bit pref] [ 0.371116] pci_bus 0000:01: resource 3 [io 0x0000-0xffff] [ 0.371119] pci_bus 0000:01: resource 4 [mem 0x00000000-0xffffffffffffffff] [ 0.371159] NET: Registered protocol family 2 [ 0.371338] IP route cache hash table entries: 65536 (order: 7, 524288 bytes) [ 0.372408] TCP established hash table entries: 262144 (order: 10, 4194304 bytes) [ 0.374840] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes) [ 0.375396] TCP: Hash tables configured (established 262144 bind 65536) [ 0.375401] TCP reno registered [ 0.375423] UDP hash table entries: 1024 (order: 3, 32768 bytes) [ 0.375450] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes) [ 0.375612] NET: Registered protocol family 1 [ 0.375643] pci 0000:00:02.0: Boot video device [ 0.375762] PCI: CLS 32 bytes, default 64 [ 0.375847] Trying to unpack rootfs image as initramfs... [ 0.649427] Freeing initrd memory: 8204k freed [ 0.654659] Scanning for low memory corruption every 60 seconds [ 0.654858] audit: initializing netlink socket (disabled) [ 0.654877] type=2000 audit(1268431036.649:1): initialized [ 0.671227] HugeTLB registered 2 MB page size, pre-allocated 0 pages [ 0.673157] VFS: Disk quotas dquot_6.5.2 [ 0.673232] Dquot-cache hash table entries: 512 (order 0, 4096 bytes) [ 0.674143] fuse init (API version 7.13) [ 0.674250] msgmni has been set to 3996 [ 0.674548] alg: No test for stdrng (krng) [ 0.674570] io scheduler noop registered [ 0.674574] io scheduler deadline registered [ 0.674669] io scheduler cfq registered (default) [ 0.674786] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 [ 0.674821] pciehp: PCI Express Hot Plug Controller Driver version: 0.4 [ 0.674996] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0 [ 0.675002] ACPI: Power Button [PWRB] [ 0.675075] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 [ 0.675079] ACPI: Power Button [PWRF] [ 0.675146] ACPI: Fan [FAN] (on) [ 0.679492] thermal LNXTHERM:01: registered as thermal_zone0 [ 0.679503] ACPI: Thermal Zone [THRM] (31 C) [ 0.681151] Linux agpgart interface v0.103 [ 0.681187] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 0.682818] brd: module loaded [ 0.683429] loop: module loaded [ 0.683545] input: Macintosh mouse button emulation as /devices/virtual/input/input2 [ 0.683708] ata_piix 0000:00:1f.1: version 2.13 [ 0.683730] alloc irq_desc for 18 on node -1 [ 0.683734] alloc kstat_irqs on node -1 [ 0.683749] ata_piix 0000:00:1f.1: PCI INT A -> GSI 18 (level, low) -> IRQ 18 [ 0.683803] ata_piix 0000:00:1f.1: setting latency timer to 64 [ 0.683939] scsi0 : ata_piix [ 0.684064] scsi1 : ata_piix [ 0.685083] ata1: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0xfa00 irq 14 [ 0.685087] ata2: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0xfa08 irq 15 [ 0.685130] alloc irq_desc for 19 on node -1 [ 0.685135] alloc kstat_irqs on node -1 [ 0.685145] ata_piix 0000:00:1f.2: PCI INT B -> GSI 19 (level, low) -> IRQ 19 [ 0.685153] ata_piix 0000:00:1f.2: MAP [ P0 P2 P1 P3 ] [ 0.685221] ata_piix 0000:00:1f.2: setting latency timer to 64 [ 0.685321] scsi2 : ata_piix [ 0.685435] scsi3 : ata_piix [ 0.686412] ata3: SATA max UDMA/133 cmd 0xf900 ctl 0xf800 bmdma 0xf500 irq 19 [ 0.686416] ata4: SATA max UDMA/133 cmd 0xf700 ctl 0xf600 bmdma 0xf508 irq 19 [ 0.687670] Fixed MDIO Bus: probed [ 0.687718] PPP generic driver version 2.4.2 [ 0.687847] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 0.687874] alloc irq_desc for 23 on node -1 [ 0.687879] alloc kstat_irqs on node -1 [ 0.687887] ehci_hcd 0000:00:1d.7: PCI INT A -> GSI 23 (level, low) -> IRQ 23 [ 0.687911] ehci_hcd 0000:00:1d.7: setting latency timer to 64 [ 0.687916] ehci_hcd 0000:00:1d.7: EHCI Host Controller [ 0.687958] ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 1 [ 0.691881] ehci_hcd 0000:00:1d.7: cache line size of 32 is not supported [ 0.691906] ehci_hcd 0000:00:1d.7: irq 23, io mem 0xfdfff000 [ 0.709761] ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00 [ 0.709908] hub 1-0:1.0: USB hub found [ 0.709916] hub 1-0:1.0: 8 ports detected [ 0.710002] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 0.710022] uhci_hcd: USB Universal Host Controller Interface driver [ 0.710104] uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 23 (level, low) -> IRQ 23 [ 0.710115] uhci_hcd 0000:00:1d.0: setting latency timer to 64 [ 0.710119] uhci_hcd 0000:00:1d.0: UHCI Host Controller [ 0.710168] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2 [ 0.710197] uhci_hcd 0000:00:1d.0: irq 23, io base 0x0000fe00 [ 0.710330] hub 2-0:1.0: USB hub found [ 0.710337] hub 2-0:1.0: 2 ports detected [ 0.710397] uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 19 (level, low) -> IRQ 19 [ 0.710405] uhci_hcd 0000:00:1d.1: setting latency timer to 64 [ 0.710409] uhci_hcd 0000:00:1d.1: UHCI Host Controller [ 0.710457] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 3 [ 0.710484] uhci_hcd 0000:00:1d.1: irq 19, io base 0x0000fd00 [ 0.710613] hub 3-0:1.0: USB hub found [ 0.710620] hub 3-0:1.0: 2 ports detected [ 0.710676] uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18 [ 0.710684] uhci_hcd 0000:00:1d.2: setting latency timer to 64 [ 0.710688] uhci_hcd 0000:00:1d.2: UHCI Host Controller [ 0.710726] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 4 [ 0.710761] uhci_hcd 0000:00:1d.2: irq 18, io base 0x0000fc00 [ 0.710891] hub 4-0:1.0: USB hub found [ 0.710897] hub 4-0:1.0: 2 ports detected [ 0.710955] alloc irq_desc for 16 on node -1 [ 0.710958] alloc kstat_irqs on node -1 [ 0.710966] uhci_hcd 0000:00:1d.3: PCI INT D -> GSI 16 (level, low) -> IRQ 16 [ 0.710973] uhci_hcd 0000:00:1d.3: setting latency timer to 64 [ 0.710977] uhci_hcd 0000:00:1d.3: UHCI Host Controller [ 0.711017] uhci_hcd 0000:00:1d.3: new USB bus registered, assigned bus number 5 [ 0.711051] uhci_hcd 0000:00:1d.3: irq 16, io base 0x0000fb00 [ 0.711183] hub 5-0:1.0: USB hub found [ 0.711190] hub 5-0:1.0: 2 ports detected [ 0.711333] PNP: No PS/2 controller found. Probing ports directly. [ 0.851363] ata1.00: ATAPI: HL-DT-STDVD-RAM GH22NP20, 1.01, max UDMA/66 [ 0.870281] ata3.00: ATA-7: SAMSUNG HD753LJ, 1AA01113, max UDMA7 [ 0.870285] ata3.00: 1465149168 sectors, multi 16: LBA48 NCQ (depth 0/32) [ 0.890160] ata1.00: configured for UDMA/66 [ 0.910140] ata3.00: configured for UDMA/133 [ 0.911813] scsi 0:0:0:0: CD-ROM HL-DT-ST DVD-RAM GH22NP20 1.01 PQ: 0 ANSI: 5 [ 0.915286] sr0: scsi3-mmc drive: 48x/48x writer dvd-ram cd/rw xa/form2 cdda tray [ 0.915291] Uniform CD-ROM driver Revision: 3.20 [ 0.915427] sr 0:0:0:0: Attached scsi CD-ROM sr0 [ 0.915491] sr 0:0:0:0: Attached scsi generic sg0 type 5 [ 0.915647] scsi 2:0:0:0: Direct-Access ATA SAMSUNG HD753LJ 1AA0 PQ: 0 ANSI: 5 [ 0.915824] sd 2:0:0:0: [sda] 1465149168 512-byte logical blocks: (750 GB/698 GiB) [ 0.915829] sd 2:0:0:0: Attached scsi generic sg1 type 0 [ 0.915946] sd 2:0:0:0: [sda] Write Protect is off [ 0.915951] sd 2:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 0.915994] sd 2:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 0.916226] sda: sda1 sda2 sda3 [ 0.950765] sd 2:0:0:0: [sda] Attached SCSI disk [ 0.960254] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 0.960372] mice: PS/2 mouse device common for all mice [ 0.960500] rtc_cmos 00:03: RTC can wake from S4 [ 0.960547] rtc_cmos 00:03: rtc core: registered rtc_cmos as rtc0 [ 0.960576] rtc0: alarms up to one month, 242 bytes nvram, hpet irqs [ 0.960772] device-mapper: uevent: version 1.0.3 [ 0.960923] device-mapper: ioctl: 4.16.0-ioctl (2009-11-05) initialised: dm-devel@redhat.com [ 0.961045] device-mapper: multipath: version 1.1.1 loaded [ 0.961049] device-mapper: multipath round-robin: version 1.0.0 loaded [ 0.961312] cpuidle: using governor ladder [ 0.961317] cpuidle: using governor menu [ 0.961801] TCP cubic registered [ 0.961978] NET: Registered protocol family 10 [ 0.962510] lo: Disabled Privacy Extensions [ 0.962860] NET: Registered protocol family 17 [ 0.962889] Bluetooth: L2CAP ver 2.14 [ 0.962891] Bluetooth: L2CAP socket layer initialized [ 0.962895] Bluetooth: SCO (Voice Link) ver 0.6 [ 0.962897] Bluetooth: SCO socket layer initialized [ 0.962961] Bluetooth: RFCOMM TTY layer initialized [ 0.962966] Bluetooth: RFCOMM socket layer initialized [ 0.962968] Bluetooth: RFCOMM ver 1.11 [ 0.963116] PM: Resume from disk failed. [ 0.963134] registered taskstats version 1 [ 0.963346] Magic number: 2:553:1005 [ 0.963367] input input2: hash matches [ 0.963405] system 00:07: hash matches [ 0.963456] rtc_cmos 00:03: setting system clock to 2010-03-12 21:57:17 UTC (1268431037) [ 0.963460] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found [ 0.963462] EDD information not available. [ 0.963527] Freeing unused kernel memory: 736k freed [ 0.963828] Write protecting the kernel read-only data: 10240k [ 0.964044] Freeing unused kernel memory: 716k freed [ 0.964600] Freeing unused kernel memory: 1608k freed [ 1.029911] usb 1-3: new high speed USB device using ehci_hcd and address 2 [ 1.127588] agpgart-intel 0000:00:00.0: Intel 915G Chipset [ 1.128052] agpgart-intel 0000:00:00.0: detected 7932K stolen memory [ 1.201185] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000 [ 1.299997] usb 1-4: new high speed USB device using ehci_hcd and address 3 [ 1.329873] [drm] Initialized drm 1.1.0 20060810 [ 1.349788] alloc irq_desc for 17 on node -1 [ 1.349794] alloc kstat_irqs on node -1 [ 1.349806] ohci1394 0000:01:05.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17 [ 1.358941] 8139cp: 10/100 PCI Ethernet driver v1.3 (Mar 22, 2004) [ 1.377914] FDC 0 is a post-1991 82077 [ 1.391124] i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 1.391132] i915 0000:00:02.0: setting latency timer to 64 [ 1.398553] [drm] set up 7M of stolen space [ 1.398803] [drm:parse_general_definitions], crt_ddc_bus_pin: 2 [ 1.398810] [drm:parse_sdvo_device_mapping], the SDVO device with slave addr 70 is found on SDVOB port [ 1.398815] [drm:parse_sdvo_device_mapping], the SDVO device with slave addr 72 is found on SDVOC port [ 1.398831] [drm:intel_modeset_init], 2 display pipes available. [ 1.399016] [drm:intel_setup_outputs], probing SDVOB [ 1.412653] ohci1394: fw-host0: OHCI-1394 1.0 (PCI): IRQ=[17] MMIO=[fddff000-fddff7ff] Max Packet=[2048] IR/IT contexts=[4/8] [ 1.419010] 8139cp 0000:01:06.0: This (id 10ec:8139 rev 10) is not an 8139C+ compatible chip, use 8139too [ 1.424757] 8139too Fast Ethernet driver 0.9.28 [ 1.424821] 8139too 0000:01:06.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18 [ 1.426361] eth0: RealTek RTL8139 at 0xec00, 00:40:ca:97:14:f4, IRQ 18 [ 1.451961] hub 1-4:1.0: USB hub found [ 1.452036] hub 1-4:1.0: 4 ports detected [ 1.647653] [drm:intel_sdvo_debug_write], SDVOB: W: 02 (SDVO_CMD_GET_DEVICE_CAPS) [ 1.684958] [drm:intel_sdvo_debug_response], SDVOB: R: 02 43 00 01 01 01 01 00 (Success) [ 1.684971] [drm:intel_sdvo_debug_write], SDVOB: W: 9D (SDVO_CMD_GET_SUPP_ENCODE) [ 1.691275] usb 1-7: new high speed USB device using ehci_hcd and address 5 [ 1.699378] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Not supported) [ 1.699446] [drm:intel_sdvo_debug_write], SDVOB: W: 10 00 (SDVO_CMD_SET_TARGET_INPUT) [ 1.709130] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 1.709141] [drm:intel_sdvo_debug_write], SDVOB: W: 1D (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE) [ 1.731185] [drm:intel_sdvo_debug_response], SDVOB: R: C4 09 20 4E (Success) [ 1.731197] [drm:intel_sdvo_init], SDVOB device VID/DID: 02:43.00, clock range 25MHz - 200MHz, input 1: Y, input 2: N, output 1: Y, output 2: N [ 1.731205] [drm:intel_setup_outputs], probing SDVOC [ 1.978345] [drm:intel_sdvo_debug_write], SDVOC: W: 02 (SDVO_CMD_GET_DEVICE_CAPS) [ 1.989754] Initializing USB Mass Storage driver... [ 1.990099] scsi4 : usb-storage 1-7:1.0 [ 1.990337] usbcore: registered new interface driver usb-storage [ 1.990341] USB Mass Storage support registered. [ 2.015833] [drm:intel_sdvo_debug_response], SDVOC: R: 02 C2 01 01 01 3D 3E 00 (Success) [ 2.015854] [drm:intel_sdvo_debug_write], SDVOC: W: 11 08 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 2.028450] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 2.028461] [drm:intel_sdvo_debug_write], SDVOC: W: 27 (SDVO_CMD_GET_SUPPORTED_TV_FORMATS) [ 2.058163] [drm:intel_sdvo_debug_response], SDVOC: R: FF FF FF FF FF 1F (Success) [ 2.058185] [drm:intel_sdvo_debug_write], SDVOC: W: 84 (SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS) [ 2.072584] [drm:intel_sdvo_debug_response], SDVOC: R: FA DF (Success) [ 2.072595] [drm:intel_sdvo_debug_write], SDVOC: W: 61 (SDVO_CMD_GET_MAX_OVERSCAN_H) [ 2.094617] [drm:intel_sdvo_debug_response], SDVOC: R: 2F 00 20 00 (Success) [ 2.094629] [drm:intel_sdvo_debug_write], SDVOC: W: 62 (SDVO_CMD_GET_OVERSCAN_H) [ 2.109018] [drm:intel_sdvo_debug_response], SDVOC: R: 20 00 (Success) [ 2.109034] [drm:intel_sdvo_create_enhance_property], h_overscan: max 47, default 32, current 32 [ 2.109040] [drm:intel_sdvo_debug_write], SDVOC: W: 64 (SDVO_CMD_GET_MAX_OVERSCAN_V) [ 2.131073] [drm:intel_sdvo_debug_response], SDVOC: R: 2F 00 20 00 (Success) [ 2.131084] [drm:intel_sdvo_debug_write], SDVOC: W: 65 (SDVO_CMD_GET_OVERSCAN_V) [ 2.145472] [drm:intel_sdvo_debug_response], SDVOC: R: 20 00 (Success) [ 2.145486] [drm:intel_sdvo_create_enhance_property], v_overscan: max 47, default 32, current 32 [ 2.145491] [drm:intel_sdvo_debug_write], SDVOC: W: 67 (SDVO_CMD_GET_MAX_POSITION_H) [ 2.167505] [drm:intel_sdvo_debug_response], SDVOC: R: FF 03 00 02 (Success) [ 2.167517] [drm:intel_sdvo_debug_write], SDVOC: W: 68 (SDVO_CMD_GET_POSITION_H) [ 2.181911] [drm:intel_sdvo_debug_response], SDVOC: R: 00 02 (Success) [ 2.181924] [drm:intel_sdvo_create_enhance_property], h_position: max 1023, default 512, current 512 [ 2.181929] [drm:intel_sdvo_debug_write], SDVOC: W: 6A (SDVO_CMD_GET_MAX_POSITION_V) [ 2.203959] [drm:intel_sdvo_debug_response], SDVOC: R: FF 03 00 02 (Success) [ 2.203971] [drm:intel_sdvo_debug_write], SDVOC: W: 6B (SDVO_CMD_GET_POSITION_V) [ 2.218349] [drm:intel_sdvo_debug_response], SDVOC: R: 00 02 (Success) [ 2.218362] [drm:intel_sdvo_create_enhance_property], v_position: max 1023, default 512, current 512 [ 2.218367] [drm:intel_sdvo_debug_write], SDVOC: W: 55 (SDVO_CMD_GET_MAX_SATURATION) [ 2.240403] [drm:intel_sdvo_debug_response], SDVOC: R: 7F 00 45 00 (Success) [ 2.240414] [drm:intel_sdvo_debug_write], SDVOC: W: 56 (SDVO_CMD_GET_SATURATION) [ 2.251270] usb 4-2: new full speed USB device using uhci_hcd and address 2 [ 2.254810] [drm:intel_sdvo_debug_response], SDVOC: R: 45 00 (Success) [ 2.254824] [drm:intel_sdvo_create_enhance_property], saturation: max 127, default 69, current 69 [ 2.254829] [drm:intel_sdvo_debug_write], SDVOC: W: 5E (SDVO_CMD_GET_MAX_CONTRAST) [ 2.276849] [drm:intel_sdvo_debug_response], SDVOC: R: 7F 00 40 00 (Success) [ 2.276861] [drm:intel_sdvo_debug_write], SDVOC: W: 5F (SDVO_CMD_GET_CONTRAST) [ 2.291274] [drm:intel_sdvo_debug_response], SDVOC: R: 40 00 (Success) [ 2.291287] [drm:intel_sdvo_create_enhance_property], contrast: max 127, default 64, current 64 [ 2.291292] [drm:intel_sdvo_debug_write], SDVOC: W: 58 (SDVO_CMD_GET_MAX_HUE) [ 2.313312] [drm:intel_sdvo_debug_response], SDVOC: R: 7F 00 40 00 (Success) [ 2.313323] [drm:intel_sdvo_debug_write], SDVOC: W: 59 (SDVO_CMD_GET_HUE) [ 2.327711] [drm:intel_sdvo_debug_response], SDVOC: R: 40 00 (Success) [ 2.327723] [drm:intel_sdvo_create_enhance_property], hue: max 127, default 64, current 64 [ 2.327728] [drm:intel_sdvo_debug_write], SDVOC: W: 5B (SDVO_CMD_GET_MAX_BRIGHTNESS) [ 2.349749] [drm:intel_sdvo_debug_response], SDVOC: R: FF 00 80 00 (Success) [ 2.349760] [drm:intel_sdvo_debug_write], SDVOC: W: 5C (SDVO_CMD_GET_BRIGHTNESS) [ 2.364158] [drm:intel_sdvo_debug_response], SDVOC: R: 80 00 (Success) [ 2.364171] [drm:intel_sdvo_create_enhance_property], brightness: max 255, default 128, current 128 [ 2.364246] [drm:intel_sdvo_debug_write], SDVOC: W: 10 00 (SDVO_CMD_SET_TARGET_INPUT) [ 2.373934] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 2.373945] [drm:intel_sdvo_debug_write], SDVOC: W: 1D (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE) [ 2.395970] [drm:intel_sdvo_debug_response], SDVOC: R: C4 09 D8 40 (Success) [ 2.395983] [drm:intel_sdvo_init], SDVOC device VID/DID: 02:C2.01, clock range 25MHz - 166MHz, input 1: Y, input 2: N, output 1: Y, output 2: N [ 2.396095] [drm] initialized overlay support [ 2.396112] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 2.408732] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 2.408744] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 2.423458] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 2.490171] [drm:drm_fb_helper_connector_parse_command_line], cmdline mode for connector VGA-1 640x480@60Hz [ 2.490180] [drm:drm_fb_helper_connector_parse_command_line], cmdline mode for connector DVI-D-1 640x480@60Hz [ 2.490187] [drm:drm_fb_helper_connector_parse_command_line], cmdline mode for connector SVIDEO-1 640x480@60Hz [ 2.490192] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 2.494649] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 2.507254] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 2.507266] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 2.519861] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 2.519873] [drm:intel_update_watermarks], plane A (pipe 0) clock: 31500 [ 2.519878] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 2.519883] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 2.519887] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 2.519890] [drm:intel_calculate_wm], FIFO watermark level: 17 [ 2.519894] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 2.519897] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 2.519900] [drm:i9xx_update_wm], FIFO watermarks - A: 17, B: 29 [ 2.519904] [drm:i9xx_update_wm], self-refresh entries: 12 [ 2.519907] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 17, B: 29, C: 2, SR 83 [ 2.540483] [drm:intel_crtc_mode_set], Mode for pipe A: [ 2.540488] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 2.570020] [drm:intel_pipe_set_base], No FB bound [ 2.570025] [drm:intel_update_watermarks], plane A (pipe 0) clock: 31500 [ 2.570029] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 2.570033] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 2.570037] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 2.570041] [drm:intel_calculate_wm], FIFO watermark level: 17 [ 2.570044] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 2.570047] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 2.570051] [drm:i9xx_update_wm], FIFO watermarks - A: 17, B: 29 [ 2.570054] [drm:i9xx_update_wm], self-refresh entries: 12 [ 2.570057] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 17, B: 29, C: 2, SR 83 [ 2.570063] [drm:intel_update_watermarks], plane A (pipe 0) clock: 31500 [ 2.570067] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 2.570071] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 2.570074] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 2.570078] [drm:intel_calculate_wm], FIFO watermark level: 17 [ 2.570081] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 2.570084] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 2.570088] [drm:i9xx_update_wm], FIFO watermarks - A: 17, B: 29 [ 2.570091] [drm:i9xx_update_wm], self-refresh entries: 12 [ 2.570094] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 17, B: 29, C: 2, SR 83 [ 2.630012] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 2.642619] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 2.642631] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 2.655233] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 2.710166] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 2.710171] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 2.710174] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 2.711271] usb 5-2: new full speed USB device using uhci_hcd and address 2 [ 2.724575] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 2.724587] [drm:intel_sdvo_detect], SDVO response 0 0 [ 2.724591] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 2.724595] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 [ 2.724599] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 2.731465] ieee1394: Host added: ID:BUS[0-00:1023] GUID[0040ca070305c6e7] [ 2.768986] [drm:intel_sdvo_debug_response], SDVOC: R: 04 00 (Success) [ 2.768999] [drm:intel_sdvo_detect], SDVO response 4 0 [ 2.769099] [drm:intel_sdvo_debug_write], SDVOC: W: 7A 01 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 2.787649] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 2.800277] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 2.800289] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 2.812889] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 2.812901] [drm:intel_update_watermarks], plane A (pipe 0) clock: 31500 [ 2.812906] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 2.812910] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 2.812914] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 2.812918] [drm:intel_calculate_wm], FIFO watermark level: 17 [ 2.812921] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 2.812924] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 2.812928] [drm:i9xx_update_wm], FIFO watermarks - A: 17, B: 29 [ 2.812931] [drm:i9xx_update_wm], self-refresh entries: 12 [ 2.812934] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 17, B: 29, C: 2, SR 83 [ 2.840467] [drm:intel_crtc_mode_set], Mode for pipe A: [ 2.840472] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 2.870028] [drm:intel_pipe_set_base], No FB bound [ 2.870033] [drm:intel_update_watermarks], plane A (pipe 0) clock: 31500 [ 2.870037] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 2.870042] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 2.870045] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 2.870049] [drm:intel_calculate_wm], FIFO watermark level: 17 [ 2.870052] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 2.870055] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 2.870059] [drm:i9xx_update_wm], FIFO watermarks - A: 17, B: 29 [ 2.870062] [drm:i9xx_update_wm], self-refresh entries: 12 [ 2.870065] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 17, B: 29, C: 2, SR 83 [ 2.870071] [drm:intel_update_watermarks], plane A (pipe 0) clock: 31500 [ 2.870075] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 2.870079] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 2.870082] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 2.870086] [drm:intel_calculate_wm], FIFO watermark level: 17 [ 2.870089] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 2.870092] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 2.870095] [drm:i9xx_update_wm], FIFO watermarks - A: 17, B: 29 [ 2.870099] [drm:i9xx_update_wm], self-refresh entries: 12 [ 2.870102] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 17, B: 29, C: 2, SR 83 [ 2.912166] usbcore: registered new interface driver hiddev [ 2.940021] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 2.952649] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 2.952661] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 2.965302] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 2.966125] generic-usb 0003:1509:925D.0001: hiddev96,hidraw0: USB HID v1.10 Device [DM-140GINK Demo DM-140GINK Demo] on usb-0000:00:1d.3-2/input0 [ 2.969199] input: DM-140GINK Demo DM-140GINK Demo as /devices/pci0000:00/0000:00:1d.3/usb5/5-2/5-2:1.1/input/input3 [ 2.969320] generic-usb 0003:1509:925D.0002: input,hidraw1: USB HID v1.10 Device [DM-140GINK Demo DM-140GINK Demo] on usb-0000:00:1d.3-2/input1 [ 2.969379] usbcore: registered new interface driver usbhid [ 2.969385] usbhid: USB HID core driver [ 2.990100] usb 1-4.4: new low speed USB device using ehci_hcd and address 7 [ 3.034611] [drm:intel_sdvo_debug_write], SDVOC: W: 11 04 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 3.047219] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.047231] [drm:intel_sdvo_debug_write], SDVOC: W: 83 01 00 00 (SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT) [ 3.074234] [drm:intel_sdvo_debug_response], SDVOC: R: FF FF 07 (Success) [ 3.074269] [drm:drm_mode_debug_printmodeline], Modeline 31:"720x400" 0 21199 720 721 784 816 400 401 432 433 0x40 0x5 [ 3.074276] [drm:drm_mode_prune_invalid], Not using 720x400 mode 16 [ 3.074281] [drm:drm_mode_debug_printmodeline], Modeline 30:"720x350" 0 18751 720 721 784 816 350 351 382 383 0x40 0x5 [ 3.074287] [drm:drm_mode_prune_invalid], Not using 720x350 mode 16 [ 3.074291] [drm:drm_mode_debug_printmodeline], Modeline 28:"704x480" 0 24624 704 705 768 800 480 481 512 513 0x40 0x5 [ 3.074296] [drm:drm_mode_prune_invalid], Not using 704x480 mode 16 [ 3.074300] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 0 22654 640 641 704 736 480 481 512 513 0x40 0x5 [ 3.074305] [drm:drm_mode_prune_invalid], Not using 640x480 mode 16 [ 3.074309] [drm:drm_mode_debug_printmodeline], Modeline 26:"640x400" 0 19121 640 641 704 736 400 401 432 433 0x40 0x5 [ 3.074315] [drm:drm_mode_prune_invalid], Not using 640x400 mode 16 [ 3.074318] [drm:drm_mode_debug_printmodeline], Modeline 25:"640x350" 0 16913 640 641 704 736 350 351 382 383 0x40 0x5 [ 3.074324] [drm:drm_mode_prune_invalid], Not using 640x350 mode 16 [ 3.074328] [drm:drm_mode_debug_printmodeline], Modeline 24:"400x300" 0 9910 400 401 464 496 300 301 332 333 0x40 0x5 [ 3.074333] [drm:drm_mode_prune_invalid], Not using 400x300 mode 16 [ 3.074337] [drm:drm_mode_debug_printmodeline], Modeline 23:"320x240" 0 6814 320 321 384 416 240 241 272 273 0x40 0x5 [ 3.074342] [drm:drm_mode_prune_invalid], Not using 320x240 mode 16 [ 3.074346] [drm:drm_mode_debug_printmodeline], Modeline 22:"320x200" 0 5815 320 321 384 416 200 201 232 233 0x40 0x5 [ 3.074351] [drm:drm_mode_prune_invalid], Not using 320x200 mode 16 [ 3.074358] [drm:drm_helper_probe_single_connector_modes], Probed modes for SVIDEO-1 [ 3.074362] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x1024" 60 87265 1280 1281 1344 1376 1024 1025 1056 1057 0x40 0x5 [ 3.074368] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 60 53827 1024 1025 1088 1120 768 769 800 801 0x40 0x5 [ 3.074374] [drm:drm_mode_debug_printmodeline], Modeline 38:"920x766" 60 48707 920 921 984 1016 766 767 798 799 0x40 0x5 [ 3.074380] [drm:drm_mode_debug_printmodeline], Modeline 37:"832x624" 60 36581 832 833 896 928 624 625 656 657 0x40 0x5 [ 3.074385] [drm:drm_mode_debug_printmodeline], Modeline 36:"800x600" 60 34030 800 801 864 896 600 601 632 633 0x40 0x5 [ 3.074391] [drm:drm_mode_debug_printmodeline], Modeline 35:"768x576" 60 31570 768 769 832 864 576 577 608 609 0x40 0x5 [ 3.074396] [drm:drm_mode_debug_printmodeline], Modeline 34:"720x576" 60 29816 720 721 784 816 576 577 608 609 0x40 0x5 [ 3.074402] [drm:drm_mode_debug_printmodeline], Modeline 29:"704x576" 60 29232 704 705 768 800 576 577 608 609 0x40 0x5 [ 3.074407] [drm:drm_mode_debug_printmodeline], Modeline 33:"720x540" 60 28054 720 721 784 816 540 541 572 573 0x40 0x5 [ 3.074413] [drm:drm_mode_debug_printmodeline], Modeline 32:"720x480" 60 25116 720 721 784 816 480 481 512 513 0x40 0x5 [ 3.074419] [drm:drm_setup_crtcs], [ 3.074423] [drm:drm_enable_connectors], connector 5 enabled? no [ 3.074427] [drm:drm_enable_connectors], connector 7 enabled? no [ 3.074430] [drm:drm_enable_connectors], connector 9 enabled? yes [ 3.074433] [drm:drm_target_preferred], looking for cmdline mode on connector 9 [ 3.074439] [drm:drm_target_preferred], found mode 640x480 [ 3.074442] [drm:drm_setup_crtcs], picking CRTCs for 4096x4096 config [ 3.074448] [drm:drm_setup_crtcs], desired mode 640x480 set on crtc 3 [ 3.074452] [drm:intelfb_probe], [ 3.076167] [drm:intelfb_create], allocated 640x480 fb: 0x007e0000, bo ffff88007afc9000 [ 3.076353] fb0: inteldrmfb frame buffer device [ 3.076356] registered panic notifier [ 3.076367] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0 [ 3.085493] [drm:drm_crtc_helper_set_config], [ 3.085501] [drm:drm_crtc_helper_set_config], crtc: ffff880037995000 3 fb: ffff88007afc93c0 connectors: ffff8800378fdf00 num_connectors: 1 (x, y) (0, 0) [ 3.085518] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set [ 3.085523] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 3.085528] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 3.085537] [drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 0 23750 640 664 720 800 480 483 487 500 0x0 0x6 [ 3.085547] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 3.085553] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 3.085557] [drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 0 23750 640 664 720 800 480 483 487 500 0x0 0x6 [ 3.085572] [drm:intel_sdvo_debug_write], SDVOC: W: 11 04 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 3.098221] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.098230] [drm:intel_sdvo_debug_write], SDVOC: W: 16 47 09 80 A0 20 E0 14 10 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1) [ 3.127285] input: 2.4G USB RF KeyBoard as /devices/pci0000:00/0000:00:1d.7/usb1/1-4/1-4.4/1-4.4:1.0/input/input4 [ 3.127416] generic-usb 0003:05AF:0319.0003: input,hidraw2: USB HID v1.10 Keyboard [2.4G USB RF KeyBoard] on usb-0000:00:1d.7-4.4/input0 [ 3.128494] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.128503] [drm:intel_sdvo_debug_write], SDVOC: W: 17 18 38 34 00 1C 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2) [ 3.131125] input: 2.4G USB RF KeyBoard as /devices/pci0000:00/0000:00:1d.7/usb1/1-4/1-4.4/1-4.4:1.1/input/input5 [ 3.131404] generic-usb 0003:05AF:0319.0004: input,hidraw3: USB HID v1.10 Mouse [2.4G USB RF KeyBoard] on usb-0000:00:1d.7-4.4/input1 [ 3.139459] input: 2.4G USB RF KeyBoard as /devices/pci0000:00/0000:00:1d.7/usb1/1-4/1-4.4/1-4.4:1.2/input/input6 [ 3.139741] generic-usb 0003:05AF:0319.0005: input,hiddev97,hidraw4: USB HID v1.10 Device [2.4G USB RF KeyBoard] on usb-0000:00:1d.7-4.4/input2 [ 3.158852] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.158861] [drm:intel_sdvo_debug_write], SDVOC: W: 10 00 (SDVO_CMD_SET_TARGET_INPUT) [ 3.168535] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.168542] [drm:intel_sdvo_debug_write], SDVOC: W: 1A 47 09 80 02 E0 01 00 (SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING) [ 3.195796] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.195804] [drm:intel_sdvo_debug_write], SDVOC: W: 1B (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1) [ 3.233097] [drm:intel_sdvo_debug_response], SDVOC: R: 8F 0E 80 90 22 E0 64 10 (Success) [ 3.233104] [drm:intel_sdvo_debug_write], SDVOC: W: 1C (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2) [ 3.270401] [drm:intel_sdvo_debug_response], SDVOC: R: A4 20 02 08 16 00 00 00 (Success) [ 3.270411] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 3.283007] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.283015] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 3.295622] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 3.295635] [drm:intel_update_watermarks], plane A (pipe 0) clock: 23750 [ 3.295641] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 3.295646] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 3.295651] [drm:intel_calculate_wm], FIFO entries required for mode: 7 [ 3.295656] [drm:intel_calculate_wm], FIFO watermark level: 19 [ 3.295660] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 3.295664] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 3.295668] [drm:i9xx_update_wm], FIFO watermarks - A: 19, B: 29 [ 3.295672] [drm:i9xx_update_wm], self-refresh entries: 9 [ 3.295676] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 19, B: 29, C: 2, SR 86 [ 3.330470] [drm:intel_crtc_mode_set], Mode for pipe A: [ 3.330474] [drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 0 37270 640 664 720 800 480 483 487 500 0x0 0x6 [ 3.360015] [drm:intel_pipe_set_base], Writing base 007E0000 00000000 0 0 [ 3.390015] [drm:intel_update_watermarks], plane A (pipe 0) clock: 23750 [ 3.390019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 3.390023] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 3.390026] [drm:intel_calculate_wm], FIFO entries required for mode: 7 [ 3.390028] [drm:intel_calculate_wm], FIFO watermark level: 19 [ 3.390031] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 3.390034] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 3.390036] [drm:i9xx_update_wm], FIFO watermarks - A: 19, B: 29 [ 3.390039] [drm:i9xx_update_wm], self-refresh entries: 9 [ 3.390041] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 19, B: 29, C: 2, SR 86 [ 3.390046] [drm:intel_sdvo_debug_write], SDVOC: W: 07 04 00 00 00 (SDVO_CMD_SET_IN_OUT_MAP) [ 3.408488] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.408496] [drm:intel_sdvo_debug_write], SDVOC: W: 10 00 (SDVO_CMD_SET_TARGET_INPUT) [ 3.418181] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.418188] [drm:intel_sdvo_debug_write], SDVOC: W: 29 01 00 00 00 00 1F (SDVO_CMD_SET_TV_FORMAT) [ 3.442511] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.442518] [drm:intel_sdvo_debug_write], SDVOC: W: 14 3C 3A 80 90 22 E0 64 10 (SDVO_CMD_SET_INPUT_TIMINGS_PART1) [ 3.472661] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.472668] [drm:intel_sdvo_debug_write], SDVOC: W: 15 A4 20 02 08 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2) [ 3.502807] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.502815] [drm:intel_sdvo_debug_write], SDVOC: W: 21 08 (SDVO_CMD_SET_CLOCK_RATE_MULT) [ 3.512486] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.512496] [drm:intel_update_watermarks], plane A (pipe 0) clock: 23750 [ 3.512500] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 3.512504] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 3.512506] [drm:intel_calculate_wm], FIFO entries required for mode: 7 [ 3.512509] [drm:intel_calculate_wm], FIFO watermark level: 19 [ 3.512512] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 3.512514] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 3.512517] [drm:i9xx_update_wm], FIFO watermarks - A: 19, B: 29 [ 3.512519] [drm:i9xx_update_wm], self-refresh entries: 9 [ 3.512522] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 19, B: 29, C: 2, SR 86 [ 3.580011] [drm:intel_sdvo_debug_write], SDVOC: W: 03 (SDVO_CMD_GET_TRAINED_INPUTS) [ 3.590578] [drm:intel_sdvo_debug_response], SDVOC: R: 01 (Success) [ 3.590586] [drm:intel_sdvo_debug_write], SDVOC: W: 05 04 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 3.603178] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.603190] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 3.615784] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 3.615791] [drm:intel_update_watermarks], plane A (pipe 0) clock: 23750 [ 3.615795] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 3.615798] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 3.615801] [drm:intel_calculate_wm], FIFO entries required for mode: 7 [ 3.615804] [drm:intel_calculate_wm], FIFO watermark level: 19 [ 3.615807] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 3.615809] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 3.615812] [drm:i9xx_update_wm], FIFO watermarks - A: 19, B: 29 [ 3.615814] [drm:i9xx_update_wm], self-refresh entries: 9 [ 3.615817] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 19, B: 29, C: 2, SR 86 [ 3.651895] Console: switching to colour frame buffer device 80x30 [ 3.651906] [drm:drm_crtc_helper_set_config], [ 3.651909] [drm:drm_crtc_helper_set_config], crtc: ffff880037995000 3 fb: ffff88007afc93c0 connectors: ffff8800378fdf00 num_connectors: 1 (x, y) (0, 0) [ 3.651919] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 3.651922] [drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 0 23750 640 664 720 800 480 483 487 500 0x0 0x6 [ 3.651928] [drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 0 37270 640 664 720 800 480 483 487 500 0x0 0x6 [ 3.651933] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 3.651937] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 3.651940] [drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 0 37270 640 664 720 800 480 483 487 500 0x0 0x6 [ 3.651948] [drm:intel_sdvo_debug_write], SDVOC: W: 11 04 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 3.664540] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.664546] [drm:intel_sdvo_debug_write], SDVOC: W: 16 8F 0E 80 A0 20 E0 14 10 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1) [ 3.694678] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.694685] [drm:intel_sdvo_debug_write], SDVOC: W: 17 18 38 34 00 1C 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2) [ 3.724833] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.724840] [drm:intel_sdvo_debug_write], SDVOC: W: 10 00 (SDVO_CMD_SET_TARGET_INPUT) [ 3.734520] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.734527] [drm:intel_sdvo_debug_write], SDVOC: W: 1A 8F 0E 80 02 E0 01 00 (SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING) [ 3.761761] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.761768] [drm:intel_sdvo_debug_write], SDVOC: W: 1B (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1) [ 3.799085] [drm:intel_sdvo_debug_response], SDVOC: R: A6 11 80 87 22 E0 6E 10 (Success) [ 3.799093] [drm:intel_sdvo_debug_write], SDVOC: W: 1C (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2) [ 3.836384] [drm:intel_sdvo_debug_response], SDVOC: R: A2 20 52 08 16 00 00 00 (Success) [ 3.836393] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 3.848987] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.848996] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 3.861609] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 3.861618] [drm:intel_update_watermarks], plane A (pipe 0) clock: 37270 [ 3.861622] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 3.861626] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 3.861628] [drm:intel_calculate_wm], FIFO entries required for mode: 11 [ 3.861631] [drm:intel_calculate_wm], FIFO watermark level: 15 [ 3.861634] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 3.861636] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 3.861639] [drm:i9xx_update_wm], FIFO watermarks - A: 15, B: 29 [ 3.861641] [drm:i9xx_update_wm], self-refresh entries: 14 [ 3.861644] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 15, B: 29, C: 2, SR 81 [ 3.890468] [drm:intel_crtc_mode_set], Mode for pipe A: [ 3.890472] [drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 0 45180 640 664 720 800 480 483 487 500 0x0 0x6 [ 3.920015] [drm:intel_pipe_set_base], Writing base 007E0000 00000000 0 0 [ 3.950014] [drm:intel_update_watermarks], plane A (pipe 0) clock: 37270 [ 3.950018] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 3.950022] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 3.950024] [drm:intel_calculate_wm], FIFO entries required for mode: 11 [ 3.950027] [drm:intel_calculate_wm], FIFO watermark level: 15 [ 3.950029] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 3.950032] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 3.950034] [drm:i9xx_update_wm], FIFO watermarks - A: 15, B: 29 [ 3.950037] [drm:i9xx_update_wm], self-refresh entries: 14 [ 3.950039] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 15, B: 29, C: 2, SR 81 [ 3.950043] [drm:intel_sdvo_debug_write], SDVOC: W: 07 04 00 00 00 (SDVO_CMD_SET_IN_OUT_MAP) [ 3.968472] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.968479] [drm:intel_sdvo_debug_write], SDVOC: W: 10 00 (SDVO_CMD_SET_TARGET_INPUT) [ 3.978151] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 3.978158] [drm:intel_sdvo_debug_write], SDVOC: W: 29 01 00 00 00 00 1F (SDVO_CMD_SET_TV_FORMAT) [ 4.002464] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.002471] [drm:intel_sdvo_debug_write], SDVOC: W: 14 98 46 80 87 22 E0 6E 10 (SDVO_CMD_SET_INPUT_TIMINGS_PART1) [ 4.032643] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.032649] [drm:intel_sdvo_debug_write], SDVOC: W: 15 A2 20 52 08 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2) [ 4.062818] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.062826] [drm:intel_sdvo_debug_write], SDVOC: W: 21 08 (SDVO_CMD_SET_CLOCK_RATE_MULT) [ 4.072499] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.072508] [drm:intel_update_watermarks], plane A (pipe 0) clock: 37270 [ 4.072512] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 4.072516] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 4.072519] [drm:intel_calculate_wm], FIFO entries required for mode: 11 [ 4.072522] [drm:intel_calculate_wm], FIFO watermark level: 15 [ 4.072524] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 4.072527] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 4.072529] [drm:i9xx_update_wm], FIFO watermarks - A: 15, B: 29 [ 4.072532] [drm:i9xx_update_wm], self-refresh entries: 14 [ 4.072534] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 15, B: 29, C: 2, SR 81 [ 4.130027] [drm:intel_sdvo_debug_write], SDVOC: W: 03 (SDVO_CMD_GET_TRAINED_INPUTS) [ 4.140595] [drm:intel_sdvo_debug_response], SDVOC: R: 01 (Success) [ 4.140602] [drm:intel_sdvo_debug_write], SDVOC: W: 05 04 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 4.153195] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.153205] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 4.165797] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 4.165804] [drm:intel_update_watermarks], plane A (pipe 0) clock: 37270 [ 4.165808] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 4.165811] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 4.165814] [drm:intel_calculate_wm], FIFO entries required for mode: 11 [ 4.165817] [drm:intel_calculate_wm], FIFO watermark level: 15 [ 4.165820] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 4.165822] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 4.165825] [drm:i9xx_update_wm], FIFO watermarks - A: 15, B: 29 [ 4.165827] [drm:i9xx_update_wm], self-refresh entries: 14 [ 4.165830] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 15, B: 29, C: 2, SR 81 [ 4.309685] [drm:drm_crtc_helper_set_config], [ 4.309690] [drm:drm_crtc_helper_set_config], crtc: ffff880037995000 3 fb: ffff88007afc93c0 connectors: ffff8800378fdf00 num_connectors: 1 (x, y) (0, 0) [ 4.309701] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 4.309705] [drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 0 37270 640 664 720 800 480 483 487 500 0x0 0x6 [ 4.309711] [drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 0 45180 640 664 720 800 480 483 487 500 0x0 0x6 [ 4.309717] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 4.309721] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 4.309724] [drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 0 45180 640 664 720 800 480 483 487 500 0x0 0x6 [ 4.309734] [drm:intel_sdvo_debug_write], SDVOC: W: 11 04 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 4.322352] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.322360] [drm:intel_sdvo_debug_write], SDVOC: W: 16 A6 11 80 A0 20 E0 14 10 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1) [ 4.352496] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.352503] [drm:intel_sdvo_debug_write], SDVOC: W: 17 18 38 34 00 1C 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2) [ 4.382638] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.382645] [drm:intel_sdvo_debug_write], SDVOC: W: 10 00 (SDVO_CMD_SET_TARGET_INPUT) [ 4.392320] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.392327] [drm:intel_sdvo_debug_write], SDVOC: W: 1A A6 11 80 02 E0 01 00 (SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING) [ 4.419540] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.419547] [drm:intel_sdvo_debug_write], SDVOC: W: 1B (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1) [ 4.456842] [drm:intel_sdvo_debug_response], SDVOC: R: A6 11 80 87 22 E0 6E 10 (Success) [ 4.456850] [drm:intel_sdvo_debug_write], SDVOC: W: 1C (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2) [ 4.494143] [drm:intel_sdvo_debug_response], SDVOC: R: A2 20 52 08 16 00 00 00 (Success) [ 4.494152] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 4.506742] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.506752] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 4.519343] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 4.519352] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 4.519357] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 4.519361] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 4.519364] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 4.519367] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 4.519370] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 4.519372] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 4.519375] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 29 [ 4.519378] [drm:i9xx_update_wm], self-refresh entries: 17 [ 4.519380] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 29, C: 2, SR 78 [ 4.541718] [drm:intel_crtc_mode_set], Mode for pipe A: [ 4.541721] [drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 0 45180 640 664 720 800 480 483 487 500 0x0 0x6 [ 4.571267] [drm:intel_pipe_set_base], Writing base 007E0000 00000000 0 0 [ 4.601264] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 4.601268] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 4.601271] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 4.601274] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 4.601277] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 4.601279] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 4.601281] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 4.601284] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 29 [ 4.601286] [drm:i9xx_update_wm], self-refresh entries: 17 [ 4.601289] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 29, C: 2, SR 78 [ 4.601294] [drm:intel_sdvo_debug_write], SDVOC: W: 07 04 00 00 00 (SDVO_CMD_SET_IN_OUT_MAP) [ 4.619721] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.619728] [drm:intel_sdvo_debug_write], SDVOC: W: 10 00 (SDVO_CMD_SET_TARGET_INPUT) [ 4.629406] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.629412] [drm:intel_sdvo_debug_write], SDVOC: W: 29 01 00 00 00 00 3F (SDVO_CMD_SET_TV_FORMAT) [ 4.653716] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.653723] [drm:intel_sdvo_debug_write], SDVOC: W: 14 98 46 80 87 22 E0 6E 10 (SDVO_CMD_SET_INPUT_TIMINGS_PART1) [ 4.683861] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.683867] [drm:intel_sdvo_debug_write], SDVOC: W: 15 A2 20 52 08 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2) [ 4.714002] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.714008] [drm:intel_sdvo_debug_write], SDVOC: W: 21 08 (SDVO_CMD_SET_CLOCK_RATE_MULT) [ 4.723680] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.723690] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 4.723693] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 4.723697] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 4.723700] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 4.723702] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 4.723705] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 4.723707] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 4.723710] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 29 [ 4.723712] [drm:i9xx_update_wm], self-refresh entries: 17 [ 4.723715] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 29, C: 2, SR 78 [ 4.780011] [drm:intel_sdvo_debug_write], SDVOC: W: 03 (SDVO_CMD_GET_TRAINED_INPUTS) [ 4.790564] [drm:intel_sdvo_debug_response], SDVOC: R: 01 (Success) [ 4.790572] [drm:intel_sdvo_debug_write], SDVOC: W: 05 04 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 4.803182] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 4.803192] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 4.815787] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 4.815794] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 4.815797] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 4.815801] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 4.815804] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 4.815806] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 4.815809] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 4.815811] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 4.815814] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 29 [ 4.815817] [drm:i9xx_update_wm], self-refresh entries: 17 [ 4.815819] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 29, C: 2, SR 78 [ 4.942867] [drm:drm_crtc_helper_set_config], [ 4.942873] [drm:drm_crtc_helper_set_config], crtc: ffff880037995000 3 fb: ffff88007afc93c0 connectors: ffff8800378fdf00 num_connectors: 1 (x, y) (0, 0) [ 4.942890] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 4.988159] PM: Starting manual resume from disk [ 4.988166] PM: Resume from partition 8:1 [ 4.988168] PM: Checking hibernation image. [ 4.988372] PM: Error -22 checking image file [ 4.988376] PM: Resume from disk failed. [ 5.049845] SGI XFS with ACLs, security attributes, realtime, large block/inode numbers, no debug enabled [ 5.051437] SGI XFS Quota Management subsystem [ 5.072371] XFS mounting filesystem sda3 [ 5.138577] Ending clean XFS mount for filesystem: sda3 [ 6.995649] scsi 4:0:0:0: Direct-Access GENERIC USB Storage-SMC I19A PQ: 0 ANSI: 0 CCS [ 6.999638] scsi 4:0:0:1: Direct-Access GENERIC USB Storage-CFC I19A PQ: 0 ANSI: 0 CCS [ 7.003638] scsi 4:0:0:2: Direct-Access GENERIC USB Storage-SDC I19A PQ: 0 ANSI: 0 CCS [ 7.007635] scsi 4:0:0:3: Direct-Access GENERIC USB Storage-MSC I19A PQ: 0 ANSI: 0 CCS [ 7.008236] sd 4:0:0:0: Attached scsi generic sg2 type 0 [ 7.008414] sd 4:0:0:1: Attached scsi generic sg3 type 0 [ 7.008588] sd 4:0:0:2: Attached scsi generic sg4 type 0 [ 7.008769] sd 4:0:0:3: Attached scsi generic sg5 type 0 [ 7.012250] sd 4:0:0:0: [sdb] Attached SCSI removable disk [ 7.013001] sd 4:0:0:1: [sdc] Attached SCSI removable disk [ 7.013750] sd 4:0:0:2: [sdd] Attached SCSI removable disk [ 7.014498] sd 4:0:0:3: [sde] Attached SCSI removable disk [ 12.892219] Adding 2441872k swap on /dev/sda1. Priority:-1 extents:1 across:2441872k [ 13.322694] udev: starting version 147 [ 13.827984] cfg80211: Calling CRDA to update world regulatory domain [ 14.711997] intel_rng: FWH not detected [ 14.759256] cfg80211: World regulatory domain updated: [ 14.759265] (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp) [ 14.759272] (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) [ 14.759278] (2457000 KHz - 2482000 KHz @ 20000 KHz), (300 mBi, 2000 mBm) [ 14.759283] (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm) [ 14.759288] (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) [ 14.759293] (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) [ 14.901303] usb 1-3: reset high speed USB device using ehci_hcd and address 2 [ 14.954628] lp: driver loaded but no devices found [ 15.194477] RPC: Registered udp transport module. [ 15.194483] RPC: Registered tcp transport module. [ 15.194487] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 15.331110] phy0: Selected rate control algorithm 'minstrel' [ 15.332050] zd1211rw 1-3:1.0: phy0 [ 15.332108] usbcore: registered new interface driver zd1211rw [ 15.355076] ip_tables: (C) 2000-2006 Netfilter Core Team [ 16.018618] HDA Intel 0000:00:1b.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 16.018681] alloc irq_desc for 24 on node -1 [ 16.018687] alloc kstat_irqs on node -1 [ 16.018707] HDA Intel 0000:00:1b.0: irq 24 for MSI/MSI-X [ 16.018802] HDA Intel 0000:00:1b.0: setting latency timer to 64 [ 16.373465] input: HDA Digital PCBeep as /devices/pci0000:00/0000:00:1b.0/input/input7 [ 17.519104] Installing knfsd (copyright (C) 1996 okir@monad.swb.de). [ 19.620433] [drm:drm_crtc_helper_set_config], [ 19.620438] [drm:drm_crtc_helper_set_config], crtc: ffff880037995000 3 fb: ffff88007afc93c0 connectors: ffff8800378fdf00 num_connectors: 1 (x, y) (0, 0) [ 19.620451] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 19.620456] [drm:drm_crtc_helper_set_config], [ 19.620459] [drm:drm_crtc_helper_set_config], crtc: ffff880037995000 3 fb: ffff88007afc93c0 connectors: ffff8800378fdf00 num_connectors: 1 (x, y) (0, 0) [ 19.620466] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 19.620483] [drm:drm_crtc_helper_set_config], [ 19.620485] [drm:drm_crtc_helper_set_config], crtc: ffff880037995000 3 fb: ffff88007afc93c0 connectors: ffff8800378fdf00 num_connectors: 1 (x, y) (0, 0) [ 19.620492] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 19.622585] [drm:drm_crtc_helper_set_config], [ 19.622592] [drm:drm_crtc_helper_set_config], crtc: ffff880037995000 3 fb: ffff88007afc93c0 connectors: ffff8800378fdf00 num_connectors: 1 (x, y) (0, 0) [ 19.622610] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 20.082240] usb 1-3: firmware: requesting zd1211/zd1211b_ub [ 20.284565] usb 1-3: firmware: requesting zd1211/zd1211b_uphr [ 20.354768] zd1211rw 1-3:1.0: firmware version 4725 [ 20.396799] zd1211rw 1-3:1.0: zd1211b chip 0586:3410 v4810 high 00-19-cb AL2230_RF pa0 g--NS [ 20.399470] cfg80211: Calling CRDA for country: DE [ 20.405059] cfg80211: Regulatory domain changed to country: DE [ 20.405065] (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp) [ 20.405069] (2400000 KHz - 2483500 KHz @ 40000 KHz), (N/A, 2000 mBm) [ 20.405072] (5150000 KHz - 5350000 KHz @ 40000 KHz), (N/A, 2000 mBm) [ 20.405075] (5470000 KHz - 5725000 KHz @ 40000 KHz), (N/A, 2698 mBm) [ 20.443973] ADDRCONF(NETDEV_UP): wlan0: link is not ready [ 20.484034] eth0: link down [ 20.484427] ADDRCONF(NETDEV_UP): eth0: link is not ready [ 21.578149] [drm:drm_crtc_helper_set_config], [ 21.578154] [drm:drm_crtc_helper_set_config], crtc: ffff880037995000 3 fb: ffff88007afc93c0 connectors: ffff8800378fdf00 num_connectors: 1 (x, y) (0, 0) [ 21.578167] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 21.956037] [drm:drm_crtc_helper_set_config], [ 21.956043] [drm:drm_crtc_helper_set_config], crtc: ffff880037995000 3 fb: ffff88007afc93c0 connectors: ffff8800378fdf00 num_connectors: 1 (x, y) (0, 0) [ 21.956059] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 23.012083] [drm:drm_crtc_helper_set_config], [ 23.012090] [drm:drm_crtc_helper_set_config], crtc: ffff880037995000 3 fb: ffff88007afc93c0 connectors: ffff8800378fdf00 num_connectors: 1 (x, y) (0, 0) [ 23.012104] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 23.012109] [drm:drm_crtc_helper_set_config], [ 23.012112] [drm:drm_crtc_helper_set_config], crtc: ffff880037996000 4 fb: ffff88007afc93c0 connectors: ffff8800378fdd00 num_connectors: 0 (x, y) (0, 0) [ 23.012120] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set [ 23.012124] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 23.012130] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 23.027588] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 23.027604] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.027610] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.027615] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.027619] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.027622] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.027626] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 23.027629] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 23.027633] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 29 [ 23.027637] [drm:i9xx_update_wm], self-refresh entries: 17 [ 23.027640] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 29, C: 2, SR 78 [ 23.051704] [drm:drm_mode_getresources], Counted 2 3 3 [ 23.051712] [drm:drm_mode_getresources], Counted 2 3 3 [ 23.051762] [drm:drm_mode_getconnector], connector id 5: [ 23.051769] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 23.056224] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 23.070046] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 23.070065] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.070071] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.070077] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.070083] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.070089] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.070094] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.070098] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.070103] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.070107] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.070113] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.091735] [drm:intel_crtc_mode_set], Mode for pipe B: [ 23.091743] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 23.121273] [drm:intel_pipe_set_base], No FB bound [ 23.121280] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.121285] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.121290] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.121295] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.121299] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.121302] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.121306] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.121310] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.121313] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.121317] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.121325] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.121329] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.121333] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.121337] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.121341] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.121345] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.121348] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.121352] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.121355] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.121359] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.181280] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 23.193954] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 23.193972] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.193978] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.193983] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.193987] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.193991] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.193994] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 23.193998] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 23.194001] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 29 [ 23.194005] [drm:i9xx_update_wm], self-refresh entries: 17 [ 23.194008] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 29, C: 2, SR 78 [ 23.221426] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 23.221447] [drm:drm_mode_getconnector], connector id 5: [ 23.221455] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 23.225910] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 23.238610] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 23.238634] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.238642] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.238649] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.238654] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.238658] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.238661] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.238665] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.238668] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.238671] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.238675] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.261881] [drm:intel_crtc_mode_set], Mode for pipe B: [ 23.261890] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 23.291281] [drm:intel_pipe_set_base], No FB bound [ 23.291289] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.291293] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.291298] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.291303] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.291307] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.291310] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.291314] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.291317] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.291321] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.291325] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.291333] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.291338] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.291342] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.291347] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.291350] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.291354] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.291357] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.291361] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.291364] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.291368] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.351277] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 23.363917] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 23.363932] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.363938] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.363942] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.363946] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.363950] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.363954] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 23.363957] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 23.363960] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 29 [ 23.363964] [drm:i9xx_update_wm], self-refresh entries: 17 [ 23.363968] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 29, C: 2, SR 78 [ 23.391434] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 23.391539] [drm:drm_mode_getconnector], connector id 7: [ 23.391545] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 23.391549] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 23.406220] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 23.406234] [drm:intel_sdvo_detect], SDVO response 0 0 [ 23.406240] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 23.406254] [drm:drm_mode_getconnector], connector id 7: [ 23.406261] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 23.406264] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 23.420724] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 23.420743] [drm:intel_sdvo_detect], SDVO response 0 0 [ 23.420750] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 23.420831] [drm:drm_mode_getconnector], connector id 9: [ 23.420839] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 [ 23.420845] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 23.465476] [drm:intel_sdvo_debug_response], SDVOC: R: 04 00 (Success) [ 23.465498] [drm:intel_sdvo_detect], SDVO response 4 0 [ 23.467631] [drm:intel_sdvo_debug_write], SDVOC: W: 7A 01 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 23.500309] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 23.519014] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 23.519035] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.519042] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.519048] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.519054] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.519060] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.519065] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.519070] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.519074] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.519079] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.519085] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.541774] [drm:intel_crtc_mode_set], Mode for pipe B: [ 23.541782] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 23.571273] [drm:intel_pipe_set_base], No FB bound [ 23.571280] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.571284] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.571289] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.571294] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.571298] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.571302] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.571305] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.571309] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.571312] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.571316] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.571324] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.571328] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.571332] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.571336] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.571340] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.571343] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.571347] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.571350] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.571354] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.571358] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.631272] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 23.643877] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 23.643896] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.643904] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.643910] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.643916] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.643922] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.643927] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 23.643932] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 23.643938] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 29 [ 23.643943] [drm:i9xx_update_wm], self-refresh entries: 17 [ 23.643948] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 29, C: 2, SR 78 [ 23.675875] [drm:intel_sdvo_debug_write], SDVOC: W: 11 04 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 23.688870] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 23.688882] [drm:intel_sdvo_debug_write], SDVOC: W: 83 01 00 00 (SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT) [ 23.716528] [drm:intel_sdvo_debug_response], SDVOC: R: FF FF 07 (Success) [ 23.716572] [drm:drm_mode_debug_printmodeline], Modeline 22:"640x480" 0 23750 640 664 720 800 480 483 487 500 0x0 0x6 [ 23.716580] [drm:drm_mode_prune_invalid], Not using 640x480 mode -3 [ 23.716585] [drm:drm_mode_debug_printmodeline], Modeline 44:"720x400" 0 21199 720 721 784 816 400 401 432 433 0x40 0x5 [ 23.716591] [drm:drm_mode_prune_invalid], Not using 720x400 mode 16 [ 23.716595] [drm:drm_mode_debug_printmodeline], Modeline 43:"720x350" 0 18751 720 721 784 816 350 351 382 383 0x40 0x5 [ 23.716601] [drm:drm_mode_prune_invalid], Not using 720x350 mode 16 [ 23.716605] [drm:drm_mode_debug_printmodeline], Modeline 41:"704x480" 0 24624 704 705 768 800 480 481 512 513 0x40 0x5 [ 23.716612] [drm:drm_mode_prune_invalid], Not using 704x480 mode 16 [ 23.716616] [drm:drm_mode_debug_printmodeline], Modeline 31:"640x480" 0 22654 640 641 704 736 480 481 512 513 0x40 0x5 [ 23.716622] [drm:drm_mode_prune_invalid], Not using 640x480 mode 16 [ 23.716626] [drm:drm_mode_debug_printmodeline], Modeline 30:"640x400" 0 19121 640 641 704 736 400 401 432 433 0x40 0x5 [ 23.716632] [drm:drm_mode_prune_invalid], Not using 640x400 mode 16 [ 23.716636] [drm:drm_mode_debug_printmodeline], Modeline 28:"640x350" 0 16913 640 641 704 736 350 351 382 383 0x40 0x5 [ 23.716642] [drm:drm_mode_prune_invalid], Not using 640x350 mode 16 [ 23.716646] [drm:drm_mode_debug_printmodeline], Modeline 27:"400x300" 0 9910 400 401 464 496 300 301 332 333 0x40 0x5 [ 23.716652] [drm:drm_mode_prune_invalid], Not using 400x300 mode 16 [ 23.716656] [drm:drm_mode_debug_printmodeline], Modeline 26:"320x240" 0 6814 320 321 384 416 240 241 272 273 0x40 0x5 [ 23.716663] [drm:drm_mode_prune_invalid], Not using 320x240 mode 16 [ 23.716667] [drm:drm_mode_debug_printmodeline], Modeline 25:"320x200" 0 5815 320 321 384 416 200 201 232 233 0x40 0x5 [ 23.716673] [drm:drm_mode_prune_invalid], Not using 320x200 mode 16 [ 23.716680] [drm:drm_helper_probe_single_connector_modes], Probed modes for SVIDEO-1 [ 23.716684] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x1024" 60 87265 1280 1281 1344 1376 1024 1025 1056 1057 0x40 0x5 [ 23.716691] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 60 53827 1024 1025 1088 1120 768 769 800 801 0x40 0x5 [ 23.716697] [drm:drm_mode_debug_printmodeline], Modeline 38:"920x766" 60 48707 920 921 984 1016 766 767 798 799 0x40 0x5 [ 23.716703] [drm:drm_mode_debug_printmodeline], Modeline 37:"832x624" 60 36581 832 833 896 928 624 625 656 657 0x40 0x5 [ 23.716709] [drm:drm_mode_debug_printmodeline], Modeline 36:"800x600" 60 34030 800 801 864 896 600 601 632 633 0x40 0x5 [ 23.716715] [drm:drm_mode_debug_printmodeline], Modeline 35:"768x576" 60 31570 768 769 832 864 576 577 608 609 0x40 0x5 [ 23.716721] [drm:drm_mode_debug_printmodeline], Modeline 34:"720x576" 60 29816 720 721 784 816 576 577 608 609 0x40 0x5 [ 23.716727] [drm:drm_mode_debug_printmodeline], Modeline 29:"704x576" 60 29232 704 705 768 800 576 577 608 609 0x40 0x5 [ 23.716733] [drm:drm_mode_debug_printmodeline], Modeline 33:"720x540" 60 28054 720 721 784 816 540 541 572 573 0x40 0x5 [ 23.716739] [drm:drm_mode_debug_printmodeline], Modeline 32:"720x480" 60 25116 720 721 784 816 480 481 512 513 0x40 0x5 [ 23.716759] [drm:drm_mode_getconnector], connector id 9: [ 23.716901] [drm:drm_mode_getconnector], connector id 5: [ 23.716907] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 23.728708] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 23.741380] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 23.741398] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.741405] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.741411] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.741417] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.741426] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.741431] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.741435] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.741440] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.741446] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.741453] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.770487] [drm:intel_crtc_mode_set], Mode for pipe B: [ 23.770494] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 23.800025] [drm:intel_pipe_set_base], No FB bound [ 23.800033] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.800038] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.800042] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.800047] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.800051] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.800055] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.800059] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.800161] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.800167] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.800173] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.800184] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.800190] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.800196] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.800202] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.800208] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.800213] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.800218] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.800224] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.800229] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.800235] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.860036] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 23.872724] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 23.872738] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.872744] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.872748] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.872752] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.872756] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.872759] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 23.872763] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 23.872766] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 29 [ 23.872770] [drm:i9xx_update_wm], self-refresh entries: 17 [ 23.872773] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 29, C: 2, SR 78 [ 23.900183] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 23.900201] [drm:drm_mode_getconnector], connector id 5: [ 23.900207] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 23.904752] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 23.917493] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 23.917515] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.917522] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.917529] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.917535] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.917541] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.917546] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.917551] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.917556] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.917561] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.917567] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.940484] [drm:intel_crtc_mode_set], Mode for pipe B: [ 23.940491] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 23.970053] [drm:intel_pipe_set_base], No FB bound [ 23.970063] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.970070] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.970079] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.970087] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.970093] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.970099] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.970104] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.970110] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.970115] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.970121] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 23.970134] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 23.970141] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 23.970147] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 23.970153] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 23.970159] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 23.970164] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 23.970169] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 23.970174] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 23.970179] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 23.970185] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 24.030024] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 24.043085] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 24.043101] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 24.043107] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 24.043111] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 24.043115] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 24.043119] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 24.043123] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 24.043126] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 24.043129] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 29 [ 24.043133] [drm:i9xx_update_wm], self-refresh entries: 17 [ 24.043136] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 29, C: 2, SR 78 [ 24.070173] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 24.114938] [drm:drm_mode_getconnector], connector id 7: [ 24.114949] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 24.114953] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 24.129385] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 24.129397] [drm:intel_sdvo_detect], SDVO response 0 0 [ 24.129402] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 24.129422] [drm:drm_mode_getconnector], connector id 7: [ 24.129428] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 24.129431] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 24.143902] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 24.143915] [drm:intel_sdvo_detect], SDVO response 0 0 [ 24.143919] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 24.143986] [drm:drm_mode_getconnector], connector id 9: [ 24.143992] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 [ 24.143996] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 24.188406] [drm:intel_sdvo_debug_response], SDVOC: R: 04 00 (Success) [ 24.188420] [drm:intel_sdvo_detect], SDVO response 4 0 [ 24.188427] [drm:intel_sdvo_debug_write], SDVOC: W: 7A 01 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 24.207950] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 24.220843] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 24.220857] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 24.220862] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 24.220867] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 24.220871] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 24.220875] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 24.220879] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 24.220883] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 24.220887] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 24.220890] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 24.220894] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 24.238564] microcode: CPU0 sig=0xf49, pf=0x10, revision=0x0 [ 24.238576] platform microcode: firmware: requesting intel-ucode/0f-04-09 [ 24.245193] [drm:intel_crtc_mode_set], Mode for pipe B: [ 24.245201] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 24.247208] microcode: CPU1 sig=0xf49, pf=0x10, revision=0x0 [ 24.247219] platform microcode: firmware: requesting intel-ucode/0f-04-09 [ 24.253588] microcode: Microcode Update Driver: v2.00 , Peter Oruba [ 24.271273] [drm:intel_pipe_set_base], No FB bound [ 24.271280] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 24.271285] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 24.271290] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 24.271295] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 24.271299] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 24.271302] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 24.271306] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 24.271309] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 24.271313] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 24.271317] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 24.271325] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 24.271329] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 24.271333] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 24.271337] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 24.271341] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 24.271344] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 24.271348] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 24.271351] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 24.271354] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 20 [ 24.271358] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 20, C: 2, SR 1 [ 24.331279] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 24.343954] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 24.343968] [drm:intel_update_watermarks], plane A (pipe 0) clock: 45180 [ 24.343974] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 24.343979] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 24.343983] [drm:intel_calculate_wm], FIFO entries required for mode: 14 [ 24.343986] [drm:intel_calculate_wm], FIFO watermark level: 12 [ 24.343990] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 24.343993] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 24.343997] [drm:i9xx_update_wm], FIFO watermarks - A: 12, B: 29 [ 24.344001] [drm:i9xx_update_wm], self-refresh entries: 17 [ 24.344004] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 12, B: 29, C: 2, SR 78 [ 24.375874] [drm:intel_sdvo_debug_write], SDVOC: W: 11 04 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 24.388618] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 24.388632] [drm:intel_sdvo_debug_write], SDVOC: W: 83 01 00 00 (SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT) [ 24.415747] [drm:intel_sdvo_debug_response], SDVOC: R: FF FF 07 (Success) [ 24.415793] [drm:drm_mode_debug_printmodeline], Modeline 43:"720x400" 0 21199 720 721 784 816 400 401 432 433 0x40 0x5 [ 24.415801] [drm:drm_mode_prune_invalid], Not using 720x400 mode 16 [ 24.415806] [drm:drm_mode_debug_printmodeline], Modeline 42:"720x350" 0 18751 720 721 784 816 350 351 382 383 0x40 0x5 [ 24.415811] [drm:drm_mode_prune_invalid], Not using 720x350 mode 16 [ 24.415815] [drm:drm_mode_debug_printmodeline], Modeline 31:"704x480" 0 24624 704 705 768 800 480 481 512 513 0x40 0x5 [ 24.415821] [drm:drm_mode_prune_invalid], Not using 704x480 mode 16 [ 24.415825] [drm:drm_mode_debug_printmodeline], Modeline 30:"640x480" 0 22654 640 641 704 736 480 481 512 513 0x40 0x5 [ 24.415830] [drm:drm_mode_prune_invalid], Not using 640x480 mode 16 [ 24.415834] [drm:drm_mode_debug_printmodeline], Modeline 28:"640x400" 0 19121 640 641 704 736 400 401 432 433 0x40 0x5 [ 24.415840] [drm:drm_mode_prune_invalid], Not using 640x400 mode 16 [ 24.415843] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x350" 0 16913 640 641 704 736 350 351 382 383 0x40 0x5 [ 24.415849] [drm:drm_mode_prune_invalid], Not using 640x350 mode 16 [ 24.415853] [drm:drm_mode_debug_printmodeline], Modeline 26:"400x300" 0 9910 400 401 464 496 300 301 332 333 0x40 0x5 [ 24.415858] [drm:drm_mode_prune_invalid], Not using 400x300 mode 16 [ 24.415862] [drm:drm_mode_debug_printmodeline], Modeline 25:"320x240" 0 6814 320 321 384 416 240 241 272 273 0x40 0x5 [ 24.415868] [drm:drm_mode_prune_invalid], Not using 320x240 mode 16 [ 24.415871] [drm:drm_mode_debug_printmodeline], Modeline 22:"320x200" 0 5815 320 321 384 416 200 201 232 233 0x40 0x5 [ 24.415877] [drm:drm_mode_prune_invalid], Not using 320x200 mode 16 [ 24.415885] [drm:drm_helper_probe_single_connector_modes], Probed modes for SVIDEO-1 [ 24.415890] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x1024" 60 87265 1280 1281 1344 1376 1024 1025 1056 1057 0x40 0x5 [ 24.415896] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 60 53827 1024 1025 1088 1120 768 769 800 801 0x40 0x5 [ 24.415902] [drm:drm_mode_debug_printmodeline], Modeline 38:"920x766" 60 48707 920 921 984 1016 766 767 798 799 0x40 0x5 [ 24.415908] [drm:drm_mode_debug_printmodeline], Modeline 37:"832x624" 60 36581 832 833 896 928 624 625 656 657 0x40 0x5 [ 24.415913] [drm:drm_mode_debug_printmodeline], Modeline 36:"800x600" 60 34030 800 801 864 896 600 601 632 633 0x40 0x5 [ 24.415919] [drm:drm_mode_debug_printmodeline], Modeline 35:"768x576" 60 31570 768 769 832 864 576 577 608 609 0x40 0x5 [ 24.415924] [drm:drm_mode_debug_printmodeline], Modeline 34:"720x576" 60 29816 720 721 784 816 576 577 608 609 0x40 0x5 [ 24.415930] [drm:drm_mode_debug_printmodeline], Modeline 29:"704x576" 60 29232 704 705 768 800 576 577 608 609 0x40 0x5 [ 24.415935] [drm:drm_mode_debug_printmodeline], Modeline 33:"720x540" 60 28054 720 721 784 816 540 541 572 573 0x40 0x5 [ 24.415941] [drm:drm_mode_debug_printmodeline], Modeline 32:"720x480" 60 25116 720 721 784 816 480 481 512 513 0x40 0x5 [ 24.415961] [drm:drm_mode_getconnector], connector id 9: [ 24.595814] [drm:drm_crtc_helper_set_config], [ 24.595822] [drm:drm_crtc_helper_set_config], crtc: ffff880037995000 3 fb: ffff88007bb07cc0 connectors: ffff88007b6f00d0 num_connectors: 1 (x, y) (0, 0) [ 24.595836] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 24.595840] [drm:drm_mode_debug_printmodeline], Modeline 24:"640x480" 0 45180 640 664 720 800 480 483 487 500 0x0 0x6 [ 24.595847] [drm:drm_mode_debug_printmodeline], Modeline 25:"1280x960" 0 108000 1280 1376 1488 1800 960 961 964 1000 0x0 0x5 [ 24.595854] [drm:drm_crtc_helper_set_config], setting connector 9 crtc to ffff880037995000 [ 24.595859] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 24.595862] [drm:drm_mode_debug_printmodeline], Modeline 25:"1280x960" 0 108000 1280 1376 1488 1800 960 961 964 1000 0x0 0x5 [ 24.595871] [drm:intel_sdvo_debug_write], SDVOC: W: 11 04 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 24.611076] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 24.611090] [drm:intel_sdvo_debug_write], SDVOC: W: 16 30 2A 00 08 52 C0 28 30 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1) [ 24.641269] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 24.641281] [drm:intel_sdvo_debug_write], SDVOC: W: 17 60 70 13 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2) [ 24.671461] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 24.671474] [drm:intel_sdvo_debug_write], SDVOC: W: 10 00 (SDVO_CMD_SET_TARGET_INPUT) [ 24.681152] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 24.681165] [drm:intel_sdvo_debug_write], SDVOC: W: 1A 30 2A 00 05 C0 03 00 (SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING) [ 24.708501] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 24.708519] [drm:intel_sdvo_debug_write], SDVOC: W: 1B (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1) [ 24.745989] [drm:intel_sdvo_debug_response], SDVOC: R: AB 2E 00 B4 51 C0 D2 30 (Success) [ 24.746010] [drm:intel_sdvo_debug_write], SDVOC: W: 1C (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2) [ 24.763665] microcode: CPU0 updated to revision 0x3, date = 2005-04-21 [ 24.766180] microcode: CPU1 updated to revision 0x3, date = 2005-04-21 [ 24.785873] [drm:intel_sdvo_debug_response], SDVOC: R: 6D 20 F2 0C 16 00 00 00 (Success) [ 24.785893] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 24.798505] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 24.798520] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 24.811147] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 24.811162] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 24.811168] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 24.811173] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 24.811177] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 24.811181] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 24.811184] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 24.811188] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 24.811191] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 24.811195] [drm:i9xx_update_wm], self-refresh entries: 43 [ 24.811198] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 24.831735] [drm:intel_crtc_mode_set], Mode for pipe A: [ 24.831742] [drm:drm_mode_debug_printmodeline], Modeline 25:"1280x960" 0 119470 1280 1376 1488 1800 960 961 964 1000 0x0 0x5 [ 24.874449] [drm:intel_pipe_set_base], Writing base 01000000 00000000 0 0 [ 24.901277] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 24.901286] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 24.901291] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 24.901295] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 24.901299] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 24.901302] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 24.901306] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 24.901309] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 24.901313] [drm:i9xx_update_wm], self-refresh entries: 43 [ 24.901317] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 24.901325] [drm:intel_sdvo_debug_write], SDVOC: W: 07 04 00 00 00 (SDVO_CMD_SET_IN_OUT_MAP) [ 24.922021] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 24.922036] [drm:intel_sdvo_debug_write], SDVOC: W: 10 00 (SDVO_CMD_SET_TARGET_INPUT) [ 24.932171] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 24.932199] [drm:intel_sdvo_debug_write], SDVOC: W: 29 01 00 00 00 00 59 (SDVO_CMD_SET_TV_FORMAT) [ 24.956854] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 24.956867] [drm:intel_sdvo_debug_write], SDVOC: W: 14 AB 2E 00 B4 51 C0 D2 30 (SDVO_CMD_SET_INPUT_TIMINGS_PART1) [ 24.987858] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 24.987871] [drm:intel_sdvo_debug_write], SDVOC: W: 15 6D 20 F2 0C 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2) [ 25.018739] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 25.018752] [drm:intel_sdvo_debug_write], SDVOC: W: 21 01 (SDVO_CMD_SET_CLOCK_RATE_MULT) [ 25.028486] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 25.028502] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 25.028508] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 25.028512] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 25.028516] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 25.028520] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 25.028524] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 25.028527] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 25.028531] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 25.028535] [drm:i9xx_update_wm], self-refresh entries: 43 [ 25.028538] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 25.080113] [drm:intel_sdvo_debug_write], SDVOC: W: 03 (SDVO_CMD_GET_TRAINED_INPUTS) [ 25.090743] [drm:intel_sdvo_debug_response], SDVOC: R: 01 (Success) [ 25.090756] [drm:intel_sdvo_debug_write], SDVOC: W: 05 04 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 25.103797] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 25.104698] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 25.117764] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 25.117790] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 25.117801] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 25.117808] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 25.117813] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 25.117818] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 25.117823] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 25.117827] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 25.117832] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 25.117837] [drm:i9xx_update_wm], self-refresh entries: 43 [ 25.117841] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 27.867915] [drm:intel_crtc_cursor_set], [ 29.580807] wlan0: direct probe to AP 00:18:39:86:e1:17 (try 1) [ 29.582914] wlan0: direct probe responded [ 29.582918] wlan0: authenticate with AP 00:18:39:86:e1:17 (try 1) [ 29.584773] wlan0: authenticated [ 29.584798] wlan0: associate with AP 00:18:39:86:e1:17 (try 1) [ 29.587047] wlan0: RX AssocResp from 00:18:39:86:e1:17 (capab=0x411 status=0 aid=3) [ 29.587051] wlan0: associated [ 29.588060] ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready [ 29.728343] Intel AES-NI instructions are not detected. [ 29.792030] padlock: VIA PadLock not detected. [ 30.467185] [drm:intel_crtc_cursor_set], [ 30.467191] [drm:intel_crtc_cursor_set], cursor off [ 33.057660] ppdev: user-space parallel port driver [ 36.295342] [drm:drm_mode_getconnector], connector id 5: [ 36.295353] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 36.299810] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 36.312484] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 36.312509] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.312516] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 36.312523] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.312530] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.312537] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.312542] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.312547] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 36.312552] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 36.312557] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 36.312563] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 36.341732] [drm:intel_crtc_mode_set], Mode for pipe B: [ 36.341740] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 36.371277] [drm:intel_pipe_set_base], No FB bound [ 36.371285] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.371290] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 36.371295] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.371299] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.371303] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.371307] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.371311] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 36.371314] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 36.371318] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 36.371322] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 36.371330] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.371334] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 36.371338] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.371342] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.371345] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.371349] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.371352] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 36.371356] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 36.371359] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 36.371363] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 36.431329] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 36.443950] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 36.443965] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.443971] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.443976] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.443980] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.443984] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.443987] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 36.443991] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 36.443994] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 36.443998] [drm:i9xx_update_wm], self-refresh entries: 43 [ 36.444001] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 36.471499] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 36.471529] [drm:drm_mode_getconnector], connector id 5: [ 36.471536] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 36.476004] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 36.488654] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 36.488671] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.488675] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 36.488680] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.488685] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.488689] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.488693] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.488696] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 36.488700] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 36.488703] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 36.488707] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 36.511734] [drm:intel_crtc_mode_set], Mode for pipe B: [ 36.511741] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 36.541675] [drm:intel_pipe_set_base], No FB bound [ 36.541684] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.541692] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 36.541793] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.541803] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.541809] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.541815] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.541820] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 36.541825] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 36.541830] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 36.541836] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 36.541847] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.541853] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 36.541858] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.541864] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.541869] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.541874] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.541879] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 36.541884] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 36.541889] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 36.541895] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 36.600043] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 36.612783] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 36.612800] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.612806] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.612811] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.612815] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.612819] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.612823] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 36.612826] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 36.612830] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 36.612834] [drm:i9xx_update_wm], self-refresh entries: 43 [ 36.612837] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 36.640179] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 36.640250] [drm:drm_mode_getconnector], connector id 7: [ 36.640257] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 36.640261] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 36.655607] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 36.655632] [drm:intel_sdvo_detect], SDVO response 0 0 [ 36.655644] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 36.656535] [drm:drm_mode_getconnector], connector id 7: [ 36.656548] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 36.656557] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 36.672039] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 36.672054] [drm:intel_sdvo_detect], SDVO response 0 0 [ 36.672059] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 36.672192] [drm:drm_mode_getconnector], connector id 9: [ 36.672199] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 [ 36.672204] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 36.716733] [drm:intel_sdvo_debug_response], SDVOC: R: 04 00 (Success) [ 36.716748] [drm:intel_sdvo_detect], SDVO response 4 0 [ 36.716755] [drm:intel_sdvo_debug_write], SDVOC: W: 7A 01 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 36.735354] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 36.747980] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 36.747994] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.748001] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 36.748011] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.748018] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.748023] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.748028] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.748033] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 36.748038] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 36.748043] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 36.748049] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 36.771738] [drm:intel_crtc_mode_set], Mode for pipe B: [ 36.771745] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 36.801350] [drm:intel_pipe_set_base], No FB bound [ 36.801361] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.801370] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 36.801378] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.801389] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.801397] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.801403] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.801409] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 36.801415] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 36.801420] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 36.801426] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 36.801438] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.801445] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 36.801452] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.801458] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.801465] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.801470] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.801475] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 36.801480] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 36.801485] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 36.801490] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 36.861277] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 36.873952] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 36.873970] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.873976] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.873981] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.873985] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.873989] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.873993] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 36.873996] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 36.874000] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 36.874004] [drm:i9xx_update_wm], self-refresh entries: 43 [ 36.874007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 36.905906] [drm:intel_sdvo_debug_write], SDVOC: W: 11 04 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 36.918974] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 36.918989] [drm:intel_sdvo_debug_write], SDVOC: W: 83 01 00 00 (SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT) [ 36.946528] [drm:intel_sdvo_debug_response], SDVOC: R: FF FF 07 (Success) [ 36.946574] [drm:drm_mode_debug_printmodeline], Modeline 45:"720x400" 0 21199 720 721 784 816 400 401 432 433 0x40 0x5 [ 36.946582] [drm:drm_mode_prune_invalid], Not using 720x400 mode 16 [ 36.946586] [drm:drm_mode_debug_printmodeline], Modeline 44:"720x350" 0 18751 720 721 784 816 350 351 382 383 0x40 0x5 [ 36.946592] [drm:drm_mode_prune_invalid], Not using 720x350 mode 16 [ 36.946596] [drm:drm_mode_debug_printmodeline], Modeline 42:"704x480" 0 24624 704 705 768 800 480 481 512 513 0x40 0x5 [ 36.946602] [drm:drm_mode_prune_invalid], Not using 704x480 mode 16 [ 36.946606] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 0 22654 640 641 704 736 480 481 512 513 0x40 0x5 [ 36.946612] [drm:drm_mode_prune_invalid], Not using 640x480 mode 16 [ 36.946616] [drm:drm_mode_debug_printmodeline], Modeline 31:"640x400" 0 19121 640 641 704 736 400 401 432 433 0x40 0x5 [ 36.946622] [drm:drm_mode_prune_invalid], Not using 640x400 mode 16 [ 36.946626] [drm:drm_mode_debug_printmodeline], Modeline 30:"640x350" 0 16913 640 641 704 736 350 351 382 383 0x40 0x5 [ 36.946631] [drm:drm_mode_prune_invalid], Not using 640x350 mode 16 [ 36.946635] [drm:drm_mode_debug_printmodeline], Modeline 28:"400x300" 0 9910 400 401 464 496 300 301 332 333 0x40 0x5 [ 36.946641] [drm:drm_mode_prune_invalid], Not using 400x300 mode 16 [ 36.946645] [drm:drm_mode_debug_printmodeline], Modeline 27:"320x240" 0 6814 320 321 384 416 240 241 272 273 0x40 0x5 [ 36.946651] [drm:drm_mode_prune_invalid], Not using 320x240 mode 16 [ 36.946655] [drm:drm_mode_debug_printmodeline], Modeline 26:"320x200" 0 5815 320 321 384 416 200 201 232 233 0x40 0x5 [ 36.946661] [drm:drm_mode_prune_invalid], Not using 320x200 mode 16 [ 36.946669] [drm:drm_helper_probe_single_connector_modes], Probed modes for SVIDEO-1 [ 36.946674] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x1024" 60 87265 1280 1281 1344 1376 1024 1025 1056 1057 0x40 0x5 [ 36.946681] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 60 53827 1024 1025 1088 1120 768 769 800 801 0x40 0x5 [ 36.946687] [drm:drm_mode_debug_printmodeline], Modeline 38:"920x766" 60 48707 920 921 984 1016 766 767 798 799 0x40 0x5 [ 36.946693] [drm:drm_mode_debug_printmodeline], Modeline 37:"832x624" 60 36581 832 833 896 928 624 625 656 657 0x40 0x5 [ 36.946699] [drm:drm_mode_debug_printmodeline], Modeline 36:"800x600" 60 34030 800 801 864 896 600 601 632 633 0x40 0x5 [ 36.946704] [drm:drm_mode_debug_printmodeline], Modeline 35:"768x576" 60 31570 768 769 832 864 576 577 608 609 0x40 0x5 [ 36.946710] [drm:drm_mode_debug_printmodeline], Modeline 34:"720x576" 60 29816 720 721 784 816 576 577 608 609 0x40 0x5 [ 36.946716] [drm:drm_mode_debug_printmodeline], Modeline 29:"704x576" 60 29232 704 705 768 800 576 577 608 609 0x40 0x5 [ 36.946721] [drm:drm_mode_debug_printmodeline], Modeline 33:"720x540" 60 28054 720 721 784 816 540 541 572 573 0x40 0x5 [ 36.946727] [drm:drm_mode_debug_printmodeline], Modeline 32:"720x480" 60 25116 720 721 784 816 480 481 512 513 0x40 0x5 [ 36.946759] [drm:drm_mode_getconnector], connector id 9: [ 36.960755] [drm:drm_mode_getconnector], connector id 5: [ 36.960765] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 36.965223] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 36.977876] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 36.977893] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 36.977898] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 36.977903] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 36.977908] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 36.977912] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 36.977915] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 36.977919] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 36.977923] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 36.977926] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 36.977930] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.000580] [drm:intel_crtc_mode_set], Mode for pipe B: [ 37.000590] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 37.031279] [drm:intel_pipe_set_base], No FB bound [ 37.031286] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.031291] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.031296] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.031300] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.031304] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.031308] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.031312] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.031315] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.031319] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.031323] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.031331] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.031336] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.031341] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.031345] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.031349] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.031352] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.031356] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.031359] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.031362] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.031366] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.091281] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 37.103903] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 37.103919] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.103924] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.103929] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.103933] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.103937] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.103940] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 37.103944] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 37.103947] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 37.103951] [drm:i9xx_update_wm], self-refresh entries: 43 [ 37.103955] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 37.131440] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 37.131471] [drm:drm_mode_getconnector], connector id 5: [ 37.131478] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 37.135932] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 37.148593] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 37.148611] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.148615] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.148620] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.148625] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.148629] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.148633] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.148637] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.148640] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.148644] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.148648] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.171882] [drm:intel_crtc_mode_set], Mode for pipe B: [ 37.171891] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 37.201277] [drm:intel_pipe_set_base], No FB bound [ 37.201284] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.201289] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.201294] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.201299] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.201303] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.201306] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.201310] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.201313] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.201317] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.201321] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.201329] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.201334] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.201338] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.201343] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.201346] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.201350] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.201353] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.201357] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.201360] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.201364] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.261285] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 37.273924] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 37.273947] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.273956] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.273963] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.273970] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.273977] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.273983] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 37.273988] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 37.273993] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 37.273998] [drm:i9xx_update_wm], self-refresh entries: 43 [ 37.274002] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 37.301432] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 37.301506] [drm:drm_mode_getconnector], connector id 7: [ 37.301513] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 37.301517] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 37.316026] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 37.316049] [drm:intel_sdvo_detect], SDVO response 0 0 [ 37.316059] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 37.316080] [drm:drm_mode_getconnector], connector id 7: [ 37.316089] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 37.316095] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 37.330811] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 37.330837] [drm:intel_sdvo_detect], SDVO response 0 0 [ 37.330848] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 37.330983] [drm:drm_mode_getconnector], connector id 9: [ 37.330995] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 [ 37.331005] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 37.390515] [drm:intel_sdvo_debug_response], SDVOC: R: 04 00 (Success) [ 37.390537] [drm:intel_sdvo_detect], SDVO response 4 0 [ 37.390830] [drm:intel_sdvo_debug_write], SDVOC: W: 7A 01 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 37.410381] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 37.423643] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 37.423672] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.423682] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.423690] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.423697] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.423705] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.423711] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.423718] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.423724] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.423729] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.423734] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.452056] [drm:intel_crtc_mode_set], Mode for pipe B: [ 37.452066] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 37.481324] [drm:intel_pipe_set_base], No FB bound [ 37.481332] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.481336] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.481341] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.481346] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.481350] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.481354] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.481358] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.481361] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.481365] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.481369] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.481377] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.481382] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.481386] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.481391] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.481394] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.481398] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.481401] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.481405] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.481408] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.481412] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.541277] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 37.553914] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 37.553931] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.553937] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.553941] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.553945] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.553949] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.553953] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 37.553956] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 37.553960] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 37.553963] [drm:i9xx_update_wm], self-refresh entries: 43 [ 37.553967] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 37.585971] [drm:intel_sdvo_debug_write], SDVOC: W: 11 04 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 37.600422] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 37.600443] [drm:intel_sdvo_debug_write], SDVOC: W: 83 01 00 00 (SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT) [ 37.628662] [drm:intel_sdvo_debug_response], SDVOC: R: FF FF 07 (Success) [ 37.628730] [drm:drm_mode_debug_printmodeline], Modeline 45:"720x400" 0 21199 720 721 784 816 400 401 432 433 0x40 0x5 [ 37.628742] [drm:drm_mode_prune_invalid], Not using 720x400 mode 16 [ 37.628748] [drm:drm_mode_debug_printmodeline], Modeline 44:"720x350" 0 18751 720 721 784 816 350 351 382 383 0x40 0x5 [ 37.628760] [drm:drm_mode_prune_invalid], Not using 720x350 mode 16 [ 37.628767] [drm:drm_mode_debug_printmodeline], Modeline 42:"704x480" 0 24624 704 705 768 800 480 481 512 513 0x40 0x5 [ 37.628777] [drm:drm_mode_prune_invalid], Not using 704x480 mode 16 [ 37.628783] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 0 22654 640 641 704 736 480 481 512 513 0x40 0x5 [ 37.628793] [drm:drm_mode_prune_invalid], Not using 640x480 mode 16 [ 37.628800] [drm:drm_mode_debug_printmodeline], Modeline 31:"640x400" 0 19121 640 641 704 736 400 401 432 433 0x40 0x5 [ 37.628810] [drm:drm_mode_prune_invalid], Not using 640x400 mode 16 [ 37.628817] [drm:drm_mode_debug_printmodeline], Modeline 30:"640x350" 0 16913 640 641 704 736 350 351 382 383 0x40 0x5 [ 37.628827] [drm:drm_mode_prune_invalid], Not using 640x350 mode 16 [ 37.628834] [drm:drm_mode_debug_printmodeline], Modeline 28:"400x300" 0 9910 400 401 464 496 300 301 332 333 0x40 0x5 [ 37.628845] [drm:drm_mode_prune_invalid], Not using 400x300 mode 16 [ 37.628852] [drm:drm_mode_debug_printmodeline], Modeline 27:"320x240" 0 6814 320 321 384 416 240 241 272 273 0x40 0x5 [ 37.628862] [drm:drm_mode_prune_invalid], Not using 320x240 mode 16 [ 37.628869] [drm:drm_mode_debug_printmodeline], Modeline 26:"320x200" 0 5815 320 321 384 416 200 201 232 233 0x40 0x5 [ 37.628879] [drm:drm_mode_prune_invalid], Not using 320x200 mode 16 [ 37.628890] [drm:drm_helper_probe_single_connector_modes], Probed modes for SVIDEO-1 [ 37.628897] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x1024" 60 87265 1280 1281 1344 1376 1024 1025 1056 1057 0x40 0x5 [ 37.628908] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 60 53827 1024 1025 1088 1120 768 769 800 801 0x40 0x5 [ 37.628918] [drm:drm_mode_debug_printmodeline], Modeline 38:"920x766" 60 48707 920 921 984 1016 766 767 798 799 0x40 0x5 [ 37.628927] [drm:drm_mode_debug_printmodeline], Modeline 37:"832x624" 60 36581 832 833 896 928 624 625 656 657 0x40 0x5 [ 37.628937] [drm:drm_mode_debug_printmodeline], Modeline 36:"800x600" 60 34030 800 801 864 896 600 601 632 633 0x40 0x5 [ 37.628947] [drm:drm_mode_debug_printmodeline], Modeline 35:"768x576" 60 31570 768 769 832 864 576 577 608 609 0x40 0x5 [ 37.628958] [drm:drm_mode_debug_printmodeline], Modeline 34:"720x576" 60 29816 720 721 784 816 576 577 608 609 0x40 0x5 [ 37.628967] [drm:drm_mode_debug_printmodeline], Modeline 29:"704x576" 60 29232 704 705 768 800 576 577 608 609 0x40 0x5 [ 37.628977] [drm:drm_mode_debug_printmodeline], Modeline 33:"720x540" 60 28054 720 721 784 816 540 541 572 573 0x40 0x5 [ 37.628986] [drm:drm_mode_debug_printmodeline], Modeline 32:"720x480" 60 25116 720 721 784 816 480 481 512 513 0x40 0x5 [ 37.629032] [drm:drm_mode_getconnector], connector id 9: [ 37.680346] [drm:drm_mode_getconnector], connector id 5: [ 37.680356] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 37.684819] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 37.697490] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 37.697506] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.697511] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.697516] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.697521] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.697525] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.697529] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.697532] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.697536] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.697539] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.697543] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.720712] [drm:intel_crtc_mode_set], Mode for pipe B: [ 37.720722] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 37.750488] [drm:intel_pipe_set_base], No FB bound [ 37.750496] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.750501] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.750506] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.750510] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.750514] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.750518] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.750522] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.750525] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.750529] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.750533] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.750540] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.750544] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.750548] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.750552] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.750556] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.750560] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.750563] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.750567] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.750570] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.750574] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.810070] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 37.823606] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 37.823624] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.823630] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.823635] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.823639] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.823643] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.823646] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 37.823650] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 37.823653] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 37.823657] [drm:i9xx_update_wm], self-refresh entries: 43 [ 37.823661] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 37.851439] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 37.851470] [drm:drm_mode_getconnector], connector id 5: [ 37.851477] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 37.855932] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 37.868583] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 37.868597] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.868602] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.868607] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.868612] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.868616] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.868619] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.868623] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.868626] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.868630] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.868634] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.891731] [drm:intel_crtc_mode_set], Mode for pipe B: [ 37.891737] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 37.921285] [drm:intel_pipe_set_base], No FB bound [ 37.921293] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.921299] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.921305] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.921311] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.921317] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.921324] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.921331] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.921335] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.921340] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.921346] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.921357] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.921365] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 37.921371] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.921375] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.921378] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.921382] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.921385] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 37.921389] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 37.921392] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 37.921396] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 37.981280] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 37.993897] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 37.993911] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 37.993917] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 37.993922] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 37.993926] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 37.993929] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 37.993933] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 37.993936] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 37.993940] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 37.993944] [drm:i9xx_update_wm], self-refresh entries: 43 [ 37.993947] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 38.021433] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 38.021501] [drm:drm_mode_getconnector], connector id 7: [ 38.021509] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 38.021513] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 38.035946] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 38.035960] [drm:intel_sdvo_detect], SDVO response 0 0 [ 38.035965] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 38.035979] [drm:drm_mode_getconnector], connector id 7: [ 38.035985] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 38.035989] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 38.050639] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 38.050653] [drm:intel_sdvo_detect], SDVO response 0 0 [ 38.050659] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 38.050734] [drm:drm_mode_getconnector], connector id 9: [ 38.050741] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 [ 38.050746] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 38.099708] [drm:intel_sdvo_debug_response], SDVOC: R: 04 00 (Success) [ 38.099732] [drm:intel_sdvo_detect], SDVO response 4 0 [ 38.099742] [drm:intel_sdvo_debug_write], SDVOC: W: 7A 01 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 38.119721] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 38.133277] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 38.133300] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 38.133306] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 38.133313] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 38.133320] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 38.133326] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 38.133332] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 38.133337] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 38.133342] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 38.133347] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 38.133353] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 38.160590] [drm:intel_crtc_mode_set], Mode for pipe B: [ 38.160598] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 38.190052] [drm:intel_pipe_set_base], No FB bound [ 38.190060] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 38.190065] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 38.190070] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 38.190075] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 38.190079] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 38.190082] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 38.190086] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 38.190089] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 38.190093] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 38.190097] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 38.190105] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 38.190109] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 38.190113] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 38.190117] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 38.190121] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 38.190124] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 38.190128] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 38.190132] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 38.190135] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 38.190139] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 38.250084] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 38.262996] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 38.263020] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 38.263029] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 38.263036] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 38.263042] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 38.263048] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 38.263054] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 38.263059] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 38.263064] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 38.263070] [drm:i9xx_update_wm], self-refresh entries: 43 [ 38.263075] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 38.294747] [drm:intel_sdvo_debug_write], SDVOC: W: 11 04 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 38.308021] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 38.308043] [drm:intel_sdvo_debug_write], SDVOC: W: 83 01 00 00 (SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT) [ 38.336579] [drm:intel_sdvo_debug_response], SDVOC: R: FF FF 07 (Success) [ 38.336674] [drm:drm_mode_debug_printmodeline], Modeline 45:"720x400" 0 21199 720 721 784 816 400 401 432 433 0x40 0x5 [ 38.336685] [drm:drm_mode_prune_invalid], Not using 720x400 mode 16 [ 38.336692] [drm:drm_mode_debug_printmodeline], Modeline 44:"720x350" 0 18751 720 721 784 816 350 351 382 383 0x40 0x5 [ 38.336701] [drm:drm_mode_prune_invalid], Not using 720x350 mode 16 [ 38.336707] [drm:drm_mode_debug_printmodeline], Modeline 42:"704x480" 0 24624 704 705 768 800 480 481 512 513 0x40 0x5 [ 38.336716] [drm:drm_mode_prune_invalid], Not using 704x480 mode 16 [ 38.336723] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 0 22654 640 641 704 736 480 481 512 513 0x40 0x5 [ 38.336733] [drm:drm_mode_prune_invalid], Not using 640x480 mode 16 [ 38.336739] [drm:drm_mode_debug_printmodeline], Modeline 31:"640x400" 0 19121 640 641 704 736 400 401 432 433 0x40 0x5 [ 38.336749] [drm:drm_mode_prune_invalid], Not using 640x400 mode 16 [ 38.336756] [drm:drm_mode_debug_printmodeline], Modeline 30:"640x350" 0 16913 640 641 704 736 350 351 382 383 0x40 0x5 [ 38.336765] [drm:drm_mode_prune_invalid], Not using 640x350 mode 16 [ 38.336772] [drm:drm_mode_debug_printmodeline], Modeline 28:"400x300" 0 9910 400 401 464 496 300 301 332 333 0x40 0x5 [ 38.336781] [drm:drm_mode_prune_invalid], Not using 400x300 mode 16 [ 38.336787] [drm:drm_mode_debug_printmodeline], Modeline 27:"320x240" 0 6814 320 321 384 416 240 241 272 273 0x40 0x5 [ 38.336797] [drm:drm_mode_prune_invalid], Not using 320x240 mode 16 [ 38.336803] [drm:drm_mode_debug_printmodeline], Modeline 26:"320x200" 0 5815 320 321 384 416 200 201 232 233 0x40 0x5 [ 38.336815] [drm:drm_mode_prune_invalid], Not using 320x200 mode 16 [ 38.336826] [drm:drm_helper_probe_single_connector_modes], Probed modes for SVIDEO-1 [ 38.336832] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x1024" 60 87265 1280 1281 1344 1376 1024 1025 1056 1057 0x40 0x5 [ 38.336843] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 60 53827 1024 1025 1088 1120 768 769 800 801 0x40 0x5 [ 38.336852] [drm:drm_mode_debug_printmodeline], Modeline 38:"920x766" 60 48707 920 921 984 1016 766 767 798 799 0x40 0x5 [ 38.336861] [drm:drm_mode_debug_printmodeline], Modeline 37:"832x624" 60 36581 832 833 896 928 624 625 656 657 0x40 0x5 [ 38.336870] [drm:drm_mode_debug_printmodeline], Modeline 36:"800x600" 60 34030 800 801 864 896 600 601 632 633 0x40 0x5 [ 38.336879] [drm:drm_mode_debug_printmodeline], Modeline 35:"768x576" 60 31570 768 769 832 864 576 577 608 609 0x40 0x5 [ 38.336889] [drm:drm_mode_debug_printmodeline], Modeline 34:"720x576" 60 29816 720 721 784 816 576 577 608 609 0x40 0x5 [ 38.336900] [drm:drm_mode_debug_printmodeline], Modeline 29:"704x576" 60 29232 704 705 768 800 576 577 608 609 0x40 0x5 [ 38.336908] [drm:drm_mode_debug_printmodeline], Modeline 33:"720x540" 60 28054 720 721 784 816 540 541 572 573 0x40 0x5 [ 38.336917] [drm:drm_mode_debug_printmodeline], Modeline 32:"720x480" 60 25116 720 721 784 816 480 481 512 513 0x40 0x5 [ 38.336968] [drm:drm_mode_getconnector], connector id 9: [ 40.160034] usb 1-7: reset high speed USB device using ehci_hcd and address 5 [ 40.430044] wlan0: no IPv6 routers present [ 43.060489] [drm:intel_crtc_cursor_set], [ 43.175765] [drm:intel_crtc_cursor_set], [ 43.175774] [drm:intel_crtc_cursor_set], cursor off [ 43.845272] [drm:intel_crtc_cursor_set], [ 48.160061] usb 1-7: reset high speed USB device using ehci_hcd and address 5 [ 53.833639] [drm:intel_crtc_cursor_set], [ 53.833646] [drm:intel_crtc_cursor_set], cursor off [ 54.059599] [drm:drm_mode_getconnector], connector id 5: [ 54.059613] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 54.064131] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 54.076803] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 54.076816] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 54.076821] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 54.076826] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 54.076831] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 54.076835] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 54.076838] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 54.076842] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 54.076845] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 54.076849] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 54.076853] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 54.101729] [drm:intel_crtc_mode_set], Mode for pipe B: [ 54.101735] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 54.131273] [drm:intel_pipe_set_base], No FB bound [ 54.131277] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 54.131281] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 54.131286] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 54.131290] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 54.131294] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 54.131298] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 54.131302] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 54.131305] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 54.131309] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 54.131312] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 54.131318] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 54.131322] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 54.131326] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 54.131330] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 54.131334] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 54.131337] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 54.131341] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 54.131344] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 54.131348] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 54.131351] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 54.191687] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 54.204348] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 54.204362] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 54.204367] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 54.204372] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 54.204375] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 54.204379] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 54.204383] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 54.204386] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 54.204390] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 54.204393] [drm:i9xx_update_wm], self-refresh entries: 43 [ 54.204396] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 54.231424] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 54.231452] [drm:drm_mode_getconnector], connector id 5: [ 54.231458] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 54.235909] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 54.248659] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 54.248671] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 54.248675] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 54.248680] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 54.248684] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 54.248688] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 54.248691] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 54.248695] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 54.248698] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 54.248701] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 54.248705] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 54.271729] [drm:intel_crtc_mode_set], Mode for pipe B: [ 54.271734] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 54.301271] [drm:intel_pipe_set_base], No FB bound [ 54.301275] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 54.301279] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 54.301284] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 54.301288] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 54.301292] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 54.301295] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 54.301299] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 54.301302] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 54.301305] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 54.301309] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 54.301315] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 54.301320] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 54.301324] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 54.301328] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 54.301332] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 54.301335] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 54.301339] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 54.301342] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 54.301345] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 54.301349] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 54.361270] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 54.373915] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 54.373928] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 54.373933] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 54.373937] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 54.373941] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 54.373944] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 54.373948] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 54.373951] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 54.373954] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 54.373958] [drm:i9xx_update_wm], self-refresh entries: 43 [ 54.373961] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 54.401424] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 54.401483] [drm:drm_mode_getconnector], connector id 7: [ 54.401489] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 54.401493] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 54.416050] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 54.416072] [drm:intel_sdvo_detect], SDVO response 0 0 [ 54.416082] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 54.416098] [drm:drm_mode_getconnector], connector id 7: [ 54.416106] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 54.416115] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 54.430741] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 54.430753] [drm:intel_sdvo_detect], SDVO response 0 0 [ 54.430757] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 54.430802] [drm:drm_mode_getconnector], connector id 9: [ 54.430807] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 [ 54.430812] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 54.475449] [drm:intel_sdvo_debug_response], SDVOC: R: 04 00 (Success) [ 54.475466] [drm:intel_sdvo_detect], SDVO response 4 0 [ 54.475474] [drm:intel_sdvo_debug_write], SDVOC: W: 7A 01 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 54.495096] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 54.507818] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 54.507835] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 54.507841] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 54.507847] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 54.507853] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 54.507858] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 54.507864] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 54.507868] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 54.507873] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 54.507878] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 54.507883] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 54.531731] [drm:intel_crtc_mode_set], Mode for pipe B: [ 54.531737] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 54.561271] [drm:intel_pipe_set_base], No FB bound [ 54.561276] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 54.561280] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 54.561285] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 54.561289] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 54.561293] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 54.561296] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 54.561300] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 54.561303] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 54.561307] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 54.561311] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 54.561318] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 54.561322] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 54.561326] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 54.561330] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 54.561334] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 54.561338] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 54.561341] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 54.561344] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 54.561348] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 54.561351] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 54.621272] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 54.633915] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 54.633928] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 54.633933] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 54.633937] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 54.633941] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 54.633944] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 54.633948] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 54.633951] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 54.633954] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 54.633958] [drm:i9xx_update_wm], self-refresh entries: 43 [ 54.633961] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 54.665869] [drm:intel_sdvo_debug_write], SDVOC: W: 11 04 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 54.678530] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 54.678541] [drm:intel_sdvo_debug_write], SDVOC: W: 83 01 00 00 (SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT) [ 54.705638] [drm:intel_sdvo_debug_response], SDVOC: R: FF FF 07 (Success) [ 54.705679] [drm:drm_mode_debug_printmodeline], Modeline 45:"720x400" 0 21199 720 721 784 816 400 401 432 433 0x40 0x5 [ 54.705685] [drm:drm_mode_prune_invalid], Not using 720x400 mode 16 [ 54.705690] [drm:drm_mode_debug_printmodeline], Modeline 44:"720x350" 0 18751 720 721 784 816 350 351 382 383 0x40 0x5 [ 54.705695] [drm:drm_mode_prune_invalid], Not using 720x350 mode 16 [ 54.705699] [drm:drm_mode_debug_printmodeline], Modeline 42:"704x480" 0 24624 704 705 768 800 480 481 512 513 0x40 0x5 [ 54.705705] [drm:drm_mode_prune_invalid], Not using 704x480 mode 16 [ 54.705709] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 0 22654 640 641 704 736 480 481 512 513 0x40 0x5 [ 54.705714] [drm:drm_mode_prune_invalid], Not using 640x480 mode 16 [ 54.705718] [drm:drm_mode_debug_printmodeline], Modeline 31:"640x400" 0 19121 640 641 704 736 400 401 432 433 0x40 0x5 [ 54.705724] [drm:drm_mode_prune_invalid], Not using 640x400 mode 16 [ 54.705728] [drm:drm_mode_debug_printmodeline], Modeline 30:"640x350" 0 16913 640 641 704 736 350 351 382 383 0x40 0x5 [ 54.705733] [drm:drm_mode_prune_invalid], Not using 640x350 mode 16 [ 54.705737] [drm:drm_mode_debug_printmodeline], Modeline 28:"400x300" 0 9910 400 401 464 496 300 301 332 333 0x40 0x5 [ 54.705743] [drm:drm_mode_prune_invalid], Not using 400x300 mode 16 [ 54.705746] [drm:drm_mode_debug_printmodeline], Modeline 27:"320x240" 0 6814 320 321 384 416 240 241 272 273 0x40 0x5 [ 54.705752] [drm:drm_mode_prune_invalid], Not using 320x240 mode 16 [ 54.705756] [drm:drm_mode_debug_printmodeline], Modeline 26:"320x200" 0 5815 320 321 384 416 200 201 232 233 0x40 0x5 [ 54.705761] [drm:drm_mode_prune_invalid], Not using 320x200 mode 16 [ 54.705768] [drm:drm_helper_probe_single_connector_modes], Probed modes for SVIDEO-1 [ 54.705772] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x1024" 60 87265 1280 1281 1344 1376 1024 1025 1056 1057 0x40 0x5 [ 54.705779] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 60 53827 1024 1025 1088 1120 768 769 800 801 0x40 0x5 [ 54.705784] [drm:drm_mode_debug_printmodeline], Modeline 38:"920x766" 60 48707 920 921 984 1016 766 767 798 799 0x40 0x5 [ 54.705790] [drm:drm_mode_debug_printmodeline], Modeline 37:"832x624" 60 36581 832 833 896 928 624 625 656 657 0x40 0x5 [ 54.705796] [drm:drm_mode_debug_printmodeline], Modeline 36:"800x600" 60 34030 800 801 864 896 600 601 632 633 0x40 0x5 [ 54.705802] [drm:drm_mode_debug_printmodeline], Modeline 35:"768x576" 60 31570 768 769 832 864 576 577 608 609 0x40 0x5 [ 54.705807] [drm:drm_mode_debug_printmodeline], Modeline 34:"720x576" 60 29816 720 721 784 816 576 577 608 609 0x40 0x5 [ 54.705813] [drm:drm_mode_debug_printmodeline], Modeline 29:"704x576" 60 29232 704 705 768 800 576 577 608 609 0x40 0x5 [ 54.705819] [drm:drm_mode_debug_printmodeline], Modeline 33:"720x540" 60 28054 720 721 784 816 540 541 572 573 0x40 0x5 [ 54.705825] [drm:drm_mode_debug_printmodeline], Modeline 32:"720x480" 60 25116 720 721 784 816 480 481 512 513 0x40 0x5 [ 54.705852] [drm:drm_mode_getconnector], connector id 9: [ 55.688351] [drm:drm_mode_getconnector], connector id 5: [ 55.688362] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 55.693272] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 55.706776] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 55.706802] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 55.706809] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 55.706817] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 55.706824] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 55.706831] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 55.706837] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 55.706842] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 55.706848] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 55.706853] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 55.706859] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 55.730492] [drm:intel_crtc_mode_set], Mode for pipe B: [ 55.730499] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 55.760022] [drm:intel_pipe_set_base], No FB bound [ 55.760027] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 55.760032] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 55.760036] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 55.760041] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 55.760045] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 55.760048] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 55.760052] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 55.760055] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 55.760059] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 55.760063] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 55.760070] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 55.760074] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 55.760078] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 55.760083] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 55.760086] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 55.760090] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 55.760093] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 55.760096] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 55.760100] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 55.760103] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 55.820021] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 55.832624] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 55.832637] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 55.832642] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 55.832647] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 55.832650] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 55.832654] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 55.832658] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 55.832661] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 55.832665] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 55.832668] [drm:i9xx_update_wm], self-refresh entries: 43 [ 55.832671] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 55.860172] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 55.860199] [drm:drm_mode_getconnector], connector id 5: [ 55.860205] [drm:drm_helper_probe_single_connector_modes], VGA-1 [ 55.864657] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 55.877287] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 55.877299] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 55.877303] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 55.877307] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 55.877312] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 55.877315] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 55.877319] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 55.877322] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 55.877325] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 55.877329] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 55.877333] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 55.900477] [drm:intel_crtc_mode_set], Mode for pipe B: [ 55.900482] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 55.930019] [drm:intel_pipe_set_base], No FB bound [ 55.930024] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 55.930028] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 55.930032] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 55.930036] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 55.930040] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 55.930043] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 55.930047] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 55.930050] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 55.930054] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 55.930058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 55.930063] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 55.930067] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 55.930071] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 55.930075] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 55.930078] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 55.930082] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 55.930085] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 55.930089] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 55.930092] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 55.930095] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 55.990018] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 56.002625] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 56.002639] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 56.002644] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 56.002648] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 56.002652] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 56.002655] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 56.002659] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 56.002662] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 56.002665] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 56.002669] [drm:i9xx_update_wm], self-refresh entries: 43 [ 56.002672] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 56.030172] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected [ 56.030233] [drm:drm_mode_getconnector], connector id 7: [ 56.030239] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 56.030243] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 56.044858] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 56.044870] [drm:intel_sdvo_detect], SDVO response 0 0 [ 56.044875] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 56.044912] [drm:drm_mode_getconnector], connector id 7: [ 56.044917] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 [ 56.044921] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 56.059598] [drm:intel_sdvo_debug_response], SDVOB: R: 00 00 (Success) [ 56.059609] [drm:intel_sdvo_detect], SDVO response 0 0 [ 56.059614] [drm:drm_helper_probe_single_connector_modes], DVI-D-1 is disconnected [ 56.059664] [drm:drm_mode_getconnector], connector id 9: [ 56.059669] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 [ 56.059674] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 56.104178] [drm:intel_sdvo_debug_response], SDVOC: R: 04 00 (Success) [ 56.104190] [drm:intel_sdvo_detect], SDVO response 4 0 [ 56.104195] [drm:intel_sdvo_debug_write], SDVOC: W: 7A 01 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 56.122852] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 56.135519] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 56.135532] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 56.135536] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 56.135541] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 56.135545] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 56.135549] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 56.135552] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 56.135556] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 56.135559] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 56.135562] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 56.135566] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 56.160484] [drm:intel_crtc_mode_set], Mode for pipe B: [ 56.160490] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 56.161275] usb 1-7: reset high speed USB device using ehci_hcd and address 5 [ 56.191269] [drm:intel_pipe_set_base], No FB bound [ 56.191274] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 56.191278] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 56.191283] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 56.191287] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 56.191291] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 56.191294] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 56.191298] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 56.191301] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 56.191305] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 56.191309] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 56.191314] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 56.191318] [drm:intel_update_watermarks], plane B (pipe 1) clock: 31500 [ 56.191322] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 56.191326] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 56.191330] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 56.191333] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 56.191337] [drm:intel_calculate_wm], FIFO entries required for mode: 9 [ 56.191340] [drm:intel_calculate_wm], FIFO watermark level: 20 [ 56.191344] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 20 [ 56.191347] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 20, C: 2, SR 1 [ 56.251269] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 56.263887] [drm:intel_sdvo_debug_response], SDVOB: R: (Success) [ 56.263900] [drm:intel_update_watermarks], plane A (pipe 0) clock: 108000 [ 56.263905] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 56.263910] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 56.263913] [drm:intel_calculate_wm], FIFO entries required for mode: 33 [ 56.263917] [drm:intel_calculate_wm], FIFO watermark level: -7 [ 56.263920] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 56.263924] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 56.263927] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 56.263931] [drm:i9xx_update_wm], self-refresh entries: 43 [ 56.263934] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 52 [ 56.295874] [drm:intel_sdvo_debug_write], SDVOC: W: 11 04 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 56.308500] [drm:intel_sdvo_debug_response], SDVOC: R: (Success) [ 56.308511] [drm:intel_sdvo_debug_write], SDVOC: W: 83 01 00 00 (SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT) [ 56.335603] [drm:intel_sdvo_debug_response], SDVOC: R: FF FF 07 (Success) [ 56.335658] [drm:drm_mode_debug_printmodeline], Modeline 45:"720x400" 0 21199 720 721 784 816 400 401 432 433 0x40 0x5 [ 56.335669] [drm:drm_mode_prune_invalid], Not using 720x400 mode 16 [ 56.335674] [drm:drm_mode_debug_printmodeline], Modeline 44:"720x350" 0 18751 720 721 784 816 350 351 382 383 0x40 0x5 [ 56.335683] [drm:drm_mode_prune_invalid], Not using 720x350 mode 16 [ 56.335688] [drm:drm_mode_debug_printmodeline], Modeline 42:"704x480" 0 24624 704 705 768 800 480 481 512 513 0x40 0x5 [ 56.335697] [drm:drm_mode_prune_invalid], Not using 704x480 mode 16 [ 56.335702] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 0 22654 640 641 704 736 480 481 512 513 0x40 0x5 [ 56.335710] [drm:drm_mode_prune_invalid], Not using 640x480 mode 16 [ 56.335715] [drm:drm_mode_debug_printmodeline], Modeline 31:"640x400" 0 19121 640 641 704 736 400 401 432 433 0x40 0x5 [ 56.335724] [drm:drm_mode_prune_invalid], Not using 640x400 mode 16 [ 56.335729] [drm:drm_mode_debug_printmodeline], Modeline 30:"640x350" 0 16913 640 641 704 736 350 351 382 383 0x40 0x5 [ 56.335737] [drm:drm_mode_prune_invalid], Not using 640x350 mode 16 [ 56.335742] [drm:drm_mode_debug_printmodeline], Modeline 28:"400x300" 0 9910 400 401 464 496 300 301 332 333 0x40 0x5 [ 56.335751] [drm:drm_mode_prune_invalid], Not using 400x300 mode 16 [ 56.335756] [drm:drm_mode_debug_printmodeline], Modeline 27:"320x240" 0 6814 320 321 384 416 240 241 272 273 0x40 0x5 [ 56.335764] [drm:drm_mode_prune_invalid], Not using 320x240 mode 16 [ 56.335769] [drm:drm_mode_debug_printmodeline], Modeline 26:"320x200" 0 5815 320 321 384 416 200 201 232 233 0x40 0x5 [ 56.335777] [drm:drm_mode_prune_invalid], Not using 320x200 mode 16 [ 56.335786] [drm:drm_helper_probe_single_connector_modes], Probed modes for SVIDEO-1 [ 56.335792] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x1024" 60 87265 1280 1281 1344 1376 1024 1025 1056 1057 0x40 0x5 [ 56.335801] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 60 53827 1024 1025 1088 1120 768 769 800 801 0x40 0x5 [ 56.335810] [drm:drm_mode_debug_printmodeline], Modeline 38:"920x766" 60 48707 920 921 984 1016 766 767 798 799 0x40 0x5 [ 56.335818] [drm:drm_mode_debug_printmodeline], Modeline 37:"832x624" 60 36581 832 833 896 928 624 625 656 657 0x40 0x5 [ 56.335827] [drm:drm_mode_debug_printmodeline], Modeline 36:"800x600" 60 34030 800 801 864 896 600 601 632 633 0x40 0x5 [ 56.335835] [drm:drm_mode_debug_printmodeline], Modeline 35:"768x576" 60 31570 768 769 832 864 576 577 608 609 0x40 0x5 [ 56.335844] [drm:drm_mode_debug_printmodeline], Modeline 34:"720x576" 60 29816 720 721 784 816 576 577 608 609 0x40 0x5 [ 56.335852] [drm:drm_mode_debug_printmodeline], Modeline 29:"704x576" 60 29232 704 705 768 800 576 577 608 609 0x40 0x5 [ 56.335860] [drm:drm_mode_debug_printmodeline], Modeline 33:"720x540" 60 28054 720 721 784 816 540 541 572 573 0x40 0x5 [ 56.335869] [drm:drm_mode_debug_printmodeline], Modeline 32:"720x480" 60 25116 720 721 784 816 480 481 512 513 0x40 0x5 [ 56.335922] [drm:drm_mode_getconnector], connector id 9: [ 62.021928] [drm:intel_crtc_cursor_set], [ 64.160029] usb 1-7: reset high speed USB device using ehci_hcd and address 5 [ 72.160025] usb 1-7: reset high speed USB device using ehci_hcd and address 5 [ 80.160026] usb 1-7: reset high speed USB device using ehci_hcd and address 5 [ 88.160041] usb 1-7: reset high speed USB device using ehci_hcd and address 5 [ 96.160024] usb 1-7: reset high speed USB device using ehci_hcd and address 5