Attachment 31804 Details for Bug 24314 – reg dump, eeepc 1005ha, after resume

reg dump, eeepc 1005ha, after resume

reg_dump2_after_suspend (text/plain), 9.16 KB, created by Oleksij Rempel on 2009-12-06 23:24:35 UTC

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Creator: Oleksij Rempel

Created: 2009-12-06 23:24:35 UTC

Size: 9.16 KB

patch

obsolete

>                 DCC: 0x000f0400 (single channel, XOR randomization: disabled, XOR bit: 11)
>           CHDECMISC: 0x22b97428 (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh disabled, flex disabled, ep not present)
>              C0DRB0: 0x000f0400 (0x0400)
>              C0DRB1: 0x0000000f (0x000f)
>              C0DRB2: 0x00000000 (0x0000)
>              C0DRB3: 0x01180000 (0x0000)
>              C1DRB0: 0x0e0d0d0c (0x0d0c)
>              C1DRB1: 0x0f0e0e0d (0x0e0d)
>              C1DRB2: 0x100f0f0e (0x0f0e)
>              C1DRB3: 0x0e0d100f (0x100f)
>             C0DRA01: 0x04020118 (0x0118)
>             C0DRA23: 0x00000402 (0x0402)
>             C1DRA01: 0x100f0e0d (0x0e0d)
>             C1DRA23: 0x1211100f (0x100f)
>          PGETBL_CTL: 0x7ffc0001
>   VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>       VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>           DPLL_TEST: 0x00010001 ()
>        CACHE_MODE_0: 0x00006820
>             D_STATE: 0x0000000b
>       DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>      RENCLK_GATE_D1: 0x00000000
>      RENCLK_GATE_D2: 0x00000000
>               SDVOB: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>               SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>             SDVOUDI: 0x000000ff
>              DSPARB: 0x00001d9c
>              DSPFW1: 0x00000000
>              DSPFW2: 0x00000000
>              DSPFW3: 0x00000000
>                ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
>                LVDS: 0xc0300300 (enabled, pipe B, 18 bit, 1 channel)
>                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>                DVOB: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>                DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>         DVOA_SRCDIM: 0x00000000
>         DVOB_SRCDIM: 0x00000000
>         DVOC_SRCDIM: 0x00000000
>          PP_CONTROL: 0x00000001 (power target: on)
>           PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>        PP_ON_DELAYS: 0x025807d0
>       PP_OFF_DELAYS: 0x01f407d0
>          PP_DIVISOR: 0x00251b05
>        PFIT_CONTROL: 0x00000008
>     PFIT_PGM_RATIOS: 0x00000000
>     PORT_HOTPLUG_EN: 0x06000200
>   PORT_HOTPLUG_STAT: 0x00008000
>            DSPACNTR: 0xd9000000 (enabled, pipe B)
>          DSPASTRIDE: 0x00001000 (4096 bytes)
>             DSPAPOS: 0x00000000 (0, 0)
>            DSPASIZE: 0x025703ff (1024, 600)
>            DSPABASE: 0x00c00000
>            DSPASURF: 0x00000000
>         DSPATILEOFF: 0x00000000
>           PIPEACONF: 0x00000000 (disabled, single-wide)
>            PIPEASRC: 0x00000000 (1, 1)
>           PIPEASTAT: 0x00000000 (status:)
>   PIPEA_GMCH_DATA_M: 0x00000000
>   PIPEA_GMCH_DATA_N: 0x00000000
>     PIPEA_DP_LINK_M: 0x00000000
>     PIPEA_DP_LINK_N: 0x00000000
>       CURSOR_A_BASE: 0x00000000
>    CURSOR_A_CONTROL: 0x00000000
>   CURSOR_A_POSITION: 0x00000000
>                FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>                FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>              DPLL_A: 0x04020033 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 4)
>           DPLL_A_MD: 0x00000000
>            HTOTAL_A: 0x00000000 (1 active, 1 total)
>            HBLANK_A: 0x00000000 (1 start, 1 end)
>             HSYNC_A: 0x00000000 (1 start, 1 end)
>            VTOTAL_A: 0x00000000 (1 active, 1 total)
>            VBLANK_A: 0x00000000 (1 start, 1 end)
>             VSYNC_A: 0x00000000 (1 start, 1 end)
>           BCLRPAT_A: 0x00000000
>        VSYNCSHIFT_A: 0x00000000
>            DSPBCNTR: 0x00000000 (disabled, pipe A)
>          DSPBSTRIDE: 0x00000000 (0 bytes)
>             DSPBPOS: 0x00000000 (0, 0)
>            DSPBSIZE: 0x00000000 (1, 1)
>            DSPBBASE: 0x00000000
>            DSPBSURF: 0x00000000
>         DSPBTILEOFF: 0x00000000
>           PIPEBCONF: 0x80000000 (enabled, single-wide)
>            PIPEBSRC: 0x03ff0257 (1024, 600)
>           PIPEBSTAT: 0x00000302 (status: VSYNC_INT_STATUS DLINE_COMPARE_STATUS VBLANK_INT_STATUS)
>   PIPEB_GMCH_DATA_M: 0x00000000
>   PIPEB_GMCH_DATA_N: 0x00000000
>     PIPEB_DP_LINK_M: 0x00000000
>     PIPEB_DP_LINK_N: 0x00000000
>       CURSOR_B_BASE: 0x00000000
>    CURSOR_B_CONTROL: 0x10000000
>   CURSOR_B_POSITION: 0x00d20076
>                FPB0: 0x00051008 (n = 5, m1 = 16, m2 = 8)
>                FPB1: 0x00051008 (n = 5, m1 = 16, m2 = 8)
>              DPLL_B: 0x98026000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 2, p2 = 14, SDVO mult 1)
>           DPLL_B_MD: 0x00000000
>            HTOTAL_B: 0x04e103ff (1024 active, 1250 total)
>            HBLANK_B: 0x04e103ff (1024 start, 1250 end)
>             HSYNC_B: 0x047f045c (1117 start, 1152 end)
>            VTOTAL_B: 0x02a70257 (600 active, 680 total)
>            VBLANK_B: 0x02a70257 (600 start, 680 end)
>             VSYNC_B: 0x025d0258 (601 start, 606 end)
>           BCLRPAT_B: 0x00000000
>        VSYNCSHIFT_B: 0x00000000
>   VCLK_DIVISOR_VGA0: 0x00031108
>   VCLK_DIVISOR_VGA1: 0x00031406
>       VCLK_POST_DIV: 0x00020002
>            VGACNTRL: 0x80000000 (disabled)
>              TV_CTL: 0x00000010
>              TV_DAC: 0x00000000
>            TV_CSC_Y: 0x00000000
>           TV_CSC_Y2: 0x00000000
>            TV_CSC_U: 0x00000000
>           TV_CSC_U2: 0x00000000
>            TV_CSC_V: 0x00000000
>           TV_CSC_V2: 0x00000000
>        TV_CLR_KNOBS: 0x00000000
>        TV_CLR_LEVEL: 0x00000000
>          TV_H_CTL_1: 0x00000000
>          TV_H_CTL_2: 0x00000000
>          TV_H_CTL_3: 0x00000000
>          TV_V_CTL_1: 0x00000000
>          TV_V_CTL_2: 0x00000000
>          TV_V_CTL_3: 0x00000000
>          TV_V_CTL_4: 0x00000000
>          TV_V_CTL_5: 0x00000000
>          TV_V_CTL_6: 0x00000000
>          TV_V_CTL_7: 0x00000000
>         TV_SC_CTL_1: 0x00000000
>         TV_SC_CTL_2: 0x00000000
>         TV_SC_CTL_3: 0x00000000
>          TV_WIN_POS: 0x00000000
>         TV_WIN_SIZE: 0x00000000
>     TV_FILTER_CTL_1: 0x00000000
>     TV_FILTER_CTL_2: 0x00000000
>     TV_FILTER_CTL_3: 0x00000000
>       TV_CC_CONTROL: 0x00000000
>          TV_CC_DATA: 0x00000000
>         TV_H_LUMA_0: 0x00000000
>        TV_H_LUMA_59: 0x00000000
>       TV_H_CHROMA_0: 0x00000000
>      TV_H_CHROMA_59: 0x00000000
>        FBC_CFB_BASE: 0x7f800000
>         FBC_LL_BASE: 0x3684f000
>         FBC_CONTROL: 0xc1f407e3
>         FBC_COMMAND: 0x00000000
>          FBC_STATUS: 0x60000000
>        FBC_CONTROL2: 0x00000000
>       FBC_FENCE_OFF: 0x00000000
>         FBC_MOD_NUM: 0x00000000
>             MI_MODE: 0x00000200
>        MI_ARB_STATE: 0x00000040
>      MI_RDRET_STATE: 0x00000000
>             ECOSKPD: 0x00000307
>                DP_B: 0x00000000
>      DPB_AUX_CH_CTL: 0x00000000
>    DPB_AUX_CH_DATA1: 0x00000000
>    DPB_AUX_CH_DATA2: 0x00000000
>    DPB_AUX_CH_DATA3: 0x00000000
>    DPB_AUX_CH_DATA4: 0x00000000
>    DPB_AUX_CH_DATA5: 0x00000000
>                DP_C: 0x00000000
>      DPC_AUX_CH_CTL: 0x00000000
>    DPC_AUX_CH_DATA1: 0x00000000
>    DPC_AUX_CH_DATA2: 0x00000000
>    DPC_AUX_CH_DATA3: 0x00000000
>    DPC_AUX_CH_DATA4: 0x00000000
>    DPC_AUX_CH_DATA5: 0x00000000
>                DP_D: 0x00000000
>      DPD_AUX_CH_CTL: 0x00000000
>    DPD_AUX_CH_DATA1: 0x00000000
>    DPD_AUX_CH_DATA2: 0x00000000
>    DPD_AUX_CH_DATA3: 0x00000000
>    DPD_AUX_CH_DATA4: 0x00000000
>    DPD_AUX_CH_DATA5: 0x00000000
>          AUD_CONFIG: 0x00000000
>    AUD_HDMIW_STATUS: 0x00000000
>      AUD_CONV_CHCNT: 0x00000000
>       VIDEO_DIP_CTL: 0x00000000
>       AUD_PINW_CNTR: 0x00000000
>         AUD_CNTL_ST: 0x00000000
>         AUD_PIN_CAP: 0x00000000
>        AUD_PINW_CAP: 0x00000000
>  AUD_PINW_UNSOLRESP: 0x00000000
>    AUD_OUT_DIG_CNVT: 0x00000000
>       AUD_OUT_CWCAP: 0x00000000
>         AUD_GRP_CAP: 0x00000000
>            FENCE  0: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>            FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>            FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>            FENCE  3: 0x00c00231 ( enabled, X tiled,   16 pitch, 0x00c00000 - 0x00e00000 (2048kb))
>            FENCE  4: 0x02800231 ( enabled, X tiled,   16 pitch, 0x02800000 - 0x02a00000 (2048kb))
>            FENCE  5: 0x02c00231 ( enabled, X tiled,   16 pitch, 0x02c00000 - 0x02e00000 (2048kb))
>            FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>            FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>            FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>            FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>           FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>           FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>           FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>           FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>           FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>           FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>pipe A dot 100800 n 3 m1 17 m2 8 p1 2 p2 10
>pipe B dot 51020 n 5 m1 16 m2 8 p1 2 p2 14

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Attachments on bug 24314: 30351 | 31362 | 31717 | 31727 | 31729 | 31749 | 31750 | 31751 | 31753 | 31787 | 31788 | 31789 | 31790 | 31803 | 31804 | 31805

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