Only set the bit 5 of SR01 on G4X platform
---
 src/i830_display.c |   15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

Index: xf86_video_intel/src/i830_display.c
===================================================================
--- xf86_video_intel.orig/src/i830_display.c	2009-07-17 10:57:35.000000000 +0800
+++ xf86_video_intel/src/i830_display.c	2009-08-05 14:38:41.000000000 +0800
@@ -1082,14 +1082,13 @@
     if (vgacntrl & VGA_DISP_DISABLE)
 	return;
 
-    /*
-       Set bit 5 of SR01;
-       Wait 30us;
-       */
-    OUTREG8(SRX, 1);
-    sr01 = INREG8(SRX + 1);
-    OUTREG8(SRX + 1, sr01 | (1 << 5));
-    usleep(30);
+    if (IS_G4X(pI830)) {
+	/* Set bit 5 of SR01;  Wait 30us;*/
+	OUTREG8(SRX, 1);
+	sr01 = INREG8(SRX + 1);
+	OUTREG8(SRX + 1, sr01 | (1 << 5));
+    	usleep(30);
+    }
     /* disable center mode on 965GM and G4X platform */
     if (IS_I965GM(pI830) || IS_G4X(pI830))
         vgacntrl &= ~(3 << 24);