jenkins@otc-gfxtest-icl-01:~/workspace/Leeroy/repos/mesa$ INTEL_DEBUG=fs LD_LIBRARY_PATH=/tmp/build_root/m64/lib:/tmp/build_root/m64/lib64:/tmp/build_root/m64/lib/x86_64-linux-gnu:/usr/lib:/usr/lib64:/usr/lib/x86_64-linux-gnu:/tmp/build_root/m64/lib/dri:/tmp/build_root/m64/lib64/dri:/tmp/build_root/m64/lib/x86_64-linux-gnu/dri:/usr/lib/dri:/usr/lib64/dri:/usr/lib/x86_64-linux-gnu/dri:/tmp/build_root/m64/lib/piglit/lib LIBGL_DRIVERS_PATH=/tmp/build_root/m64/lib/dri:/tmp/build_root/m64/lib64/dri:/tmp/build_root/m64/lib/x86_64-linux-gnu/dri:/usr/lib/dri:/usr/lib64/dri:/usr/lib/x86_64-linux-gnu/dri VK_ICD_FILENAMES=/tmp/build_root/m64/share/vulkan/icd.d/intel_icd.x86_64.json PIGLIT_DEBUG=1 PATH=/tmp/build_root/m64/bin:/usr/local/bin:/usr/bin:/bin:/usr/games MESA_EXTENSION_OVERRIDE="+GL_ARB_gpu_shader_fp64 +GL_ARB_vertex_attrib_64bit +GL_ARB_gpu_shader_int64 +GL_ARB_shader_ballot" DISPLAY=:0 /tmp/build_root/m64/lib/piglit/bin/shader_runner /tmp/build_root/m64/lib/piglit/tests/spec/arb_gpu_shader_int64/execution/fs-ishl-then-ushr.shader_test -auto -fbo WARNING: i965 does not fully support Gen11 yet. Instability or lower performance might occur. piglit: debug: Requested an OpenGL 4.0 Core Context, and received a matching 4.5 context GLSL IR for native fragment shader 0: ( (declare (location=1 shader_in ) vec4 gl_Color) (declare (location=2 shader_out ) vec4 gl_FragColor) ( function main (signature void (parameters ) ( (assign (xyzw) (var_ref gl_FragColor) (var_ref gl_Color) ) )) ) ) NIR (SSA form) for fragment shader: shader: MESA_SHADER_FRAGMENT name: GLSL0 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_Color (VARYING_SLOT_COL0, 1, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR, 4, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */ vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (1, 0) /* base=1 */ /* component=0 */ intrinsic store_output (ssa_2, ssa_1) (4, 15, 0) /* base=4 */ /* wrmask=xyzw */ /* component=0 */ /* gl_FragColor */ /* succs: block_1 */ block block_1: } NIR (final form) for fragment shader: shader: MESA_SHADER_FRAGMENT name: GLSL0 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_Color (VARYING_SLOT_COL0, 1, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR, 4, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */ vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (1, 0) /* base=1 */ /* component=0 */ intrinsic store_output (ssa_2, ssa_1) (4, 15, 0) /* base=4 */ /* wrmask=xyzw */ /* component=0 */ /* gl_FragColor */ /* succs: block_1 */ block block_1: } Native code for unnamed fragment shader GLSL0 SIMD8 shader: 9 instructions. 0 loops. 66 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 144 to 144 bytes (0%) START B0 (66 cycles) mad(8) acc0<1>NF g4.3<0,1,0>F g2<8,8,1>F g4.0<0,1,0>F { align1 1Q }; mad(8) g124<1>F acc0<8,8,1>NF g3<8,8,1>F g4.1<0,1,0>F { align1 1Q }; mad(8) acc0<1>NF g4.7<0,1,0>F g2<8,8,1>F g4.4<0,1,0>F { align1 1Q }; mad(8) g125<1>F acc0<8,8,1>NF g3<8,8,1>F g4.5<0,1,0>F { align1 1Q }; mad(8) acc0<1>NF g5.3<0,1,0>F g2<8,8,1>F g5.0<0,1,0>F { align1 1Q }; mad(8) g126<1>F acc0<8,8,1>NF g3<8,8,1>F g5.1<0,1,0>F { align1 1Q }; mad(8) acc0<1>NF g5.7<0,1,0>F g2<8,8,1>F g5.4<0,1,0>F { align1 1Q }; mad(8) g127<1>F acc0<8,8,1>NF g3<8,8,1>F g5.5<0,1,0>F { align1 1Q }; sendc(8) null<1>UW g124<0,1,0>F 0x88031400 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT }; END B0 Native code for unnamed fragment shader GLSL0 SIMD16 shader: 17 instructions. 0 loops. 76 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 272 to 272 bytes (0%) START B0 (76 cycles) mad(8) acc0<1>NF g6.3<0,1,0>F g2<8,8,1>F g6.0<0,1,0>F { align1 1Q }; mad(8) g120<1>F acc0<8,8,1>NF g3<8,8,1>F g6.1<0,1,0>F { align1 1Q }; mad(8) acc0<1>NF g6.3<0,1,0>F g4<8,8,1>F g6.0<0,1,0>F { align1 2Q }; mad(8) g121<1>F acc0<8,8,1>NF g5<8,8,1>F g6.1<0,1,0>F { align1 2Q }; mad(8) acc0<1>NF g6.7<0,1,0>F g2<8,8,1>F g6.4<0,1,0>F { align1 1Q }; mad(8) g122<1>F acc0<8,8,1>NF g3<8,8,1>F g6.5<0,1,0>F { align1 1Q }; mad(8) acc0<1>NF g6.7<0,1,0>F g4<8,8,1>F g6.4<0,1,0>F { align1 2Q }; mad(8) g123<1>F acc0<8,8,1>NF g5<8,8,1>F g6.5<0,1,0>F { align1 2Q }; mad(8) acc0<1>NF g7.3<0,1,0>F g2<8,8,1>F g7.0<0,1,0>F { align1 1Q }; mad(8) g124<1>F acc0<8,8,1>NF g3<8,8,1>F g7.1<0,1,0>F { align1 1Q }; mad(8) acc0<1>NF g7.3<0,1,0>F g4<8,8,1>F g7.0<0,1,0>F { align1 2Q }; mad(8) g125<1>F acc0<8,8,1>NF g5<8,8,1>F g7.1<0,1,0>F { align1 2Q }; mad(8) acc0<1>NF g7.7<0,1,0>F g2<8,8,1>F g7.4<0,1,0>F { align1 1Q }; mad(8) g126<1>F acc0<8,8,1>NF g3<8,8,1>F g7.5<0,1,0>F { align1 1Q }; mad(8) acc0<1>NF g7.7<0,1,0>F g4<8,8,1>F g7.4<0,1,0>F { align1 2Q }; mad(8) g127<1>F acc0<8,8,1>NF g5<8,8,1>F g7.5<0,1,0>F { align1 2Q }; sendc(16) null<1>UW g120<0,1,0>F 0x90031000 render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT }; END B0 GLSL IR for native fragment shader 3: ( (declare (location=0 uniform ) (array uint64_t 8) ival) (declare (location=4 shader_out ) vec4 piglit_fragcolor) ( function main (signature void (parameters ) ( (declare () uint64_t result) (declare () uint fail_mask) (assign (x) (var_ref fail_mask) (constant uint (0)) ) (assign (x) (var_ref result) (expression uint64_t >> (expression uint64_t << (array_ref (var_ref ival) (constant uint (0)) ) (constant uint (56)) ) (constant uint (56)) ) ) (declare (temporary ) uint conditional_tmp) (if (expression bool != (var_ref result) (constant uint64_t (239)) ) ( (assign (x) (var_ref conditional_tmp) (constant uint (1)) ) ) ( (assign (x) (var_ref conditional_tmp) (constant uint (0)) ) )) (assign (x) (var_ref fail_mask) (expression uint | (constant uint (0)) (var_ref conditional_tmp) ) ) (assign (x) (var_ref result) (expression uint64_t >> (expression uint64_t << (array_ref (var_ref ival) (constant uint (1)) ) (constant uint (48)) ) (constant uint (56)) ) ) (declare (temporary ) uint conditional_tmp@2) (if (expression bool != (var_ref result) (constant uint64_t (186)) ) ( (assign (x) (var_ref conditional_tmp@2) (constant uint (2)) ) ) ( (assign (x) (var_ref conditional_tmp@2) (constant uint (0)) ) )) (assign (x) (var_ref fail_mask) (expression uint | (var_ref fail_mask) (var_ref conditional_tmp@2) ) ) (assign (x) (var_ref result) (expression uint64_t >> (expression uint64_t << (array_ref (var_ref ival) (constant uint (2)) ) (constant uint (40)) ) (constant uint (56)) ) ) (declare (temporary ) uint conditional_tmp@3) (if (expression bool != (var_ref result) (constant uint64_t (245)) ) ( (assign (x) (var_ref conditional_tmp@3) (constant uint (4)) ) ) ( (assign (x) (var_ref conditional_tmp@3) (constant uint (0)) ) )) (assign (x) (var_ref fail_mask) (expression uint | (var_ref fail_mask) (var_ref conditional_tmp@3) ) ) (assign (x) (var_ref result) (expression uint64_t >> (expression uint64_t << (array_ref (var_ref ival) (constant uint (3)) ) (constant uint (32)) ) (constant uint (56)) ) ) (declare (temporary ) uint conditional_tmp@4) (if (expression bool != (var_ref result) (constant uint64_t (79)) ) ( (assign (x) (var_ref conditional_tmp@4) (constant uint (8)) ) ) ( (assign (x) (var_ref conditional_tmp@4) (constant uint (0)) ) )) (assign (x) (var_ref fail_mask) (expression uint | (var_ref fail_mask) (var_ref conditional_tmp@4) ) ) (assign (x) (var_ref result) (expression uint64_t >> (expression uint64_t << (array_ref (var_ref ival) (constant uint (4)) ) (constant uint (24)) ) (constant uint (56)) ) ) (declare (temporary ) uint conditional_tmp@5) (if (expression bool != (var_ref result) (constant uint64_t (115)) ) ( (assign (x) (var_ref conditional_tmp@5) (constant uint (16)) ) ) ( (assign (x) (var_ref conditional_tmp@5) (constant uint (0)) ) )) (assign (x) (var_ref fail_mask) (expression uint | (var_ref fail_mask) (var_ref conditional_tmp@5) ) ) (assign (x) (var_ref result) (expression uint64_t >> (expression uint64_t << (array_ref (var_ref ival) (constant uint (5)) ) (constant uint (16)) ) (constant uint (56)) ) ) (declare (temporary ) uint conditional_tmp@6) (if (expression bool != (var_ref result) (constant uint64_t (39)) ) ( (assign (x) (var_ref conditional_tmp@6) (constant uint (32)) ) ) ( (assign (x) (var_ref conditional_tmp@6) (constant uint (0)) ) )) (assign (x) (var_ref fail_mask) (expression uint | (var_ref fail_mask) (var_ref conditional_tmp@6) ) ) (assign (x) (var_ref result) (expression uint64_t >> (expression uint64_t << (array_ref (var_ref ival) (constant uint (6)) ) (constant uint (8)) ) (constant uint (56)) ) ) (declare (temporary ) uint conditional_tmp@7) (if (expression bool != (var_ref result) (constant uint64_t (46)) ) ( (assign (x) (var_ref conditional_tmp@7) (constant uint (64)) ) ) ( (assign (x) (var_ref conditional_tmp@7) (constant uint (0)) ) )) (assign (x) (var_ref fail_mask) (expression uint | (var_ref fail_mask) (var_ref conditional_tmp@7) ) ) (assign (x) (var_ref result) (expression uint64_t >> (array_ref (var_ref ival) (constant uint (7)) ) (constant uint (56)) ) ) (declare (temporary ) uint conditional_tmp@8) (if (expression bool != (var_ref result) (constant uint64_t (186)) ) ( (assign (x) (var_ref conditional_tmp@8) (constant uint (128)) ) ) ( (assign (x) (var_ref conditional_tmp@8) (constant uint (0)) ) )) (assign (x) (var_ref fail_mask) (expression uint | (var_ref fail_mask) (var_ref conditional_tmp@8) ) ) (declare (temporary ) vec4 conditional_tmp@9) (if (expression bool == (var_ref fail_mask) (constant uint (0)) ) ( (assign (xyzw) (var_ref conditional_tmp@9) (constant vec4 (0.000000 1.000000 0.000000 1.000000)) ) ) ( (declare (temporary ) vec4 vec_ctor) (assign (yzw) (var_ref vec_ctor) (constant vec3 (0.000000 0.000000 1.000000)) ) (assign (x) (var_ref vec_ctor) (expression float * (expression float u2f (var_ref fail_mask) ) (expression float rcp (constant float (255.000000)) ) ) ) (assign (xyzw) (var_ref conditional_tmp@9) (var_ref vec_ctor) ) )) (assign (xyzw) (var_ref piglit_fragcolor) (var_ref conditional_tmp@9) ) )) ) ) NIR (SSA form) for fragment shader: shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 64 shared: 0 decl_var uniform INTERP_MODE_NONE uint64_t[8] ival (0, 0, 0) = { { 0xbaddc0dedeadbeef }, { 0xdeadbea7ba5eba11 }, { 0xf0f1f2f3f4f5f6f7 }, { 0xf1f2f3f4f5f6f7f }, { 0x7071727374757677 }, { 0x717273747576777 }, { 0x1f2e3d4c5b6a7988 }, { 0xbadb100ddeadc0de } } decl_var shader_out INTERP_MODE_NONE vec4 piglit_fragcolor (FRAG_RESULT_DATA0, 8, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_2 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000010 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_8 = load_const (0x00000080 /* 0.000000 */) vec1 64 ssa_9 = intrinsic load_uniform (ssa_0) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_10 = load_const (0x 7 /* 0.000000 */) vec1 64 ssa_11 = load_const (0x 0 /* 0.000000 */) vec1 64 ssa_12 = extract_u8 ssa_9, ssa_11 vec1 32 ssa_13 = unpack_64_2x32_split_x ssa_12 vec1 32 ssa_14 = unpack_64_2x32_split_y ssa_12 vec1 32 ssa_15 = load_const (0x000000ef /* 0.000000 */) vec1 32 ssa_16 = ine32 ssa_13, ssa_15 vec1 32 ssa_17 = ine32 ssa_14, ssa_0 vec1 32 ssa_18 = ior ssa_17, ssa_16 vec1 32 ssa_19 = b32csel ssa_18, ssa_1, ssa_0 vec1 64 ssa_20 = intrinsic load_uniform (ssa_5) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_21 = load_const (0x 1 /* 0.000000 */) vec1 64 ssa_22 = extract_u8 ssa_20, ssa_21 vec1 32 ssa_23 = unpack_64_2x32_split_x ssa_22 vec1 32 ssa_24 = unpack_64_2x32_split_y ssa_22 vec1 32 ssa_25 = load_const (0x000000ba /* 0.000000 */) vec1 32 ssa_26 = ine32 ssa_23, ssa_25 vec1 32 ssa_27 = ine32 ssa_24, ssa_0 vec1 32 ssa_28 = ior ssa_27, ssa_26 vec1 32 ssa_29 = b32csel ssa_28, ssa_2, ssa_0 vec1 32 ssa_30 = ior ssa_19, ssa_29 vec1 64 ssa_31 = intrinsic load_uniform (ssa_6) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_32 = load_const (0x 2 /* 0.000000 */) vec1 64 ssa_33 = extract_u8 ssa_31, ssa_32 vec1 32 ssa_34 = unpack_64_2x32_split_x ssa_33 vec1 32 ssa_35 = unpack_64_2x32_split_y ssa_33 vec1 32 ssa_36 = load_const (0x000000f5 /* 0.000000 */) vec1 32 ssa_37 = ine32 ssa_34, ssa_36 vec1 32 ssa_38 = ine32 ssa_35, ssa_0 vec1 32 ssa_39 = ior ssa_38, ssa_37 vec1 32 ssa_40 = b32csel ssa_39, ssa_3, ssa_0 vec1 32 ssa_41 = ior ssa_30, ssa_40 vec1 32 ssa_42 = load_const (0x00000018 /* 0.000000 */) vec1 64 ssa_43 = intrinsic load_uniform (ssa_42) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_44 = load_const (0x 3 /* 0.000000 */) vec1 64 ssa_45 = extract_u8 ssa_43, ssa_44 vec1 32 ssa_46 = unpack_64_2x32_split_x ssa_45 vec1 32 ssa_47 = unpack_64_2x32_split_y ssa_45 vec1 32 ssa_48 = load_const (0x0000004f /* 0.000000 */) vec1 32 ssa_49 = ine32 ssa_46, ssa_48 vec1 32 ssa_50 = ine32 ssa_47, ssa_0 vec1 32 ssa_51 = ior ssa_50, ssa_49 vec1 32 ssa_52 = b32csel ssa_51, ssa_5, ssa_0 vec1 32 ssa_53 = ior ssa_41, ssa_52 vec1 64 ssa_54 = intrinsic load_uniform (ssa_4) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_55 = load_const (0x 4 /* 0.000000 */) vec1 64 ssa_56 = extract_u8 ssa_54, ssa_55 vec1 32 ssa_57 = unpack_64_2x32_split_x ssa_56 vec1 32 ssa_58 = unpack_64_2x32_split_y ssa_56 vec1 32 ssa_59 = load_const (0x00000073 /* 0.000000 */) vec1 32 ssa_60 = ine32 ssa_57, ssa_59 vec1 32 ssa_61 = ine32 ssa_58, ssa_0 vec1 32 ssa_62 = ior ssa_61, ssa_60 vec1 32 ssa_63 = b32csel ssa_62, ssa_6, ssa_0 vec1 32 ssa_64 = ior ssa_53, ssa_63 vec1 32 ssa_65 = load_const (0x00000028 /* 0.000000 */) vec1 64 ssa_66 = intrinsic load_uniform (ssa_65) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_67 = load_const (0x 5 /* 0.000000 */) vec1 64 ssa_68 = extract_u8 ssa_66, ssa_67 vec1 32 ssa_69 = unpack_64_2x32_split_x ssa_68 vec1 32 ssa_70 = unpack_64_2x32_split_y ssa_68 vec1 32 ssa_71 = load_const (0x00000027 /* 0.000000 */) vec1 32 ssa_72 = ine32 ssa_69, ssa_71 vec1 32 ssa_73 = ine32 ssa_70, ssa_0 vec1 32 ssa_74 = ior ssa_73, ssa_72 vec1 32 ssa_75 = b32csel ssa_74, ssa_4, ssa_0 vec1 32 ssa_76 = ior ssa_64, ssa_75 vec1 32 ssa_77 = load_const (0x00000030 /* 0.000000 */) vec1 64 ssa_78 = intrinsic load_uniform (ssa_77) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_79 = load_const (0x 6 /* 0.000000 */) vec1 64 ssa_80 = extract_u8 ssa_78, ssa_79 vec1 32 ssa_81 = unpack_64_2x32_split_x ssa_80 vec1 32 ssa_82 = unpack_64_2x32_split_y ssa_80 vec1 32 ssa_83 = load_const (0x0000002e /* 0.000000 */) vec1 32 ssa_84 = ine32 ssa_81, ssa_83 vec1 32 ssa_85 = ine32 ssa_82, ssa_0 vec1 32 ssa_86 = ior ssa_85, ssa_84 vec1 32 ssa_87 = b32csel ssa_86, ssa_7, ssa_0 vec1 32 ssa_88 = ior ssa_76, ssa_87 vec1 32 ssa_89 = load_const (0x00000038 /* 0.000000 */) vec1 64 ssa_90 = intrinsic load_uniform (ssa_89) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_91 = extract_u8 ssa_90, ssa_10 vec1 32 ssa_92 = unpack_64_2x32_split_x ssa_91 vec1 32 ssa_93 = unpack_64_2x32_split_y ssa_91 vec1 32 ssa_94 = ine32 ssa_92, ssa_25 vec1 32 ssa_95 = ine32 ssa_93, ssa_0 vec1 32 ssa_96 = ior ssa_95, ssa_94 vec1 32 ssa_97 = b32csel ssa_96, ssa_8, ssa_0 vec1 32 ssa_98 = ior ssa_88, ssa_97 vec1 32 ssa_99 = ieq32 ssa_98, ssa_0 /* succs: block_1 block_2 */ if ssa_99 { block block_1: /* preds: block_0 */ vec1 32 ssa_100 = load_const (0x3f800000 /* 1.000000 */) /* succs: block_3 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_101 = u2f32 ssa_98 vec1 32 ssa_102 = load_const (0x3b808081 /* 0.003922 */) vec1 32 ssa_103 = fmul ssa_101, ssa_102 vec1 32 ssa_104 = load_const (0x3f800000 /* 1.000000 */) /* succs: block_3 */ } block block_3: /* preds: block_1 block_2 */ vec1 32 ssa_105 = phi block_1: ssa_0, block_2: ssa_103 vec1 32 ssa_106 = phi block_1: ssa_100, block_2: ssa_0 vec1 32 ssa_107 = phi block_1: ssa_100, block_2: ssa_104 vec4 32 ssa_108 = vec4 ssa_105, ssa_106, ssa_0, ssa_107 intrinsic store_output (ssa_108, ssa_0) (8, 15, 0) /* base=8 */ /* wrmask=xyzw */ /* component=0 */ /* piglit_fragcolor */ /* succs: block_4 */ block block_4: } NIR (final form) for fragment shader: shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 64 shared: 0 decl_var uniform INTERP_MODE_NONE uint64_t[8] ival (0, 0, 0) = { { 0xbaddc0dedeadbeef }, { 0xdeadbea7ba5eba11 }, { 0xf0f1f2f3f4f5f6f7 }, { 0xf1f2f3f4f5f6f7f }, { 0x7071727374757677 }, { 0x717273747576777 }, { 0x1f2e3d4c5b6a7988 }, { 0xbadb100ddeadc0de } } decl_var shader_out INTERP_MODE_NONE vec4 piglit_fragcolor (FRAG_RESULT_DATA0, 8, 0) decl_function main (0 params) impl main { decl_reg vec1 32 r0 decl_reg vec1 32 r1 decl_reg vec1 32 r2 block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_2 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000010 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_8 = load_const (0x00000080 /* 0.000000 */) vec1 64 ssa_9 = intrinsic load_uniform (ssa_0) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_10 = load_const (0x 7 /* 0.000000 */) vec1 64 ssa_11 = load_const (0x 0 /* 0.000000 */) vec1 64 ssa_12 = extract_u8 ssa_9, ssa_11 vec1 32 ssa_13 = unpack_64_2x32_split_x ssa_12 vec1 32 ssa_14 = unpack_64_2x32_split_y ssa_12 vec1 32 ssa_15 = load_const (0x000000ef /* 0.000000 */) vec1 32 ssa_16 = ine32 ssa_13, ssa_15 vec1 32 ssa_17 = ine32 ssa_14, ssa_0 vec1 32 ssa_18 = ior ssa_17, ssa_16 vec1 32 ssa_19 = b32csel ssa_18, ssa_1, ssa_0 vec1 64 ssa_20 = intrinsic load_uniform (ssa_5) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_21 = load_const (0x 1 /* 0.000000 */) vec1 64 ssa_22 = extract_u8 ssa_20, ssa_21 vec1 32 ssa_23 = unpack_64_2x32_split_x ssa_22 vec1 32 ssa_24 = unpack_64_2x32_split_y ssa_22 vec1 32 ssa_25 = load_const (0x000000ba /* 0.000000 */) vec1 32 ssa_26 = ine32 ssa_23, ssa_25 vec1 32 ssa_27 = ine32 ssa_24, ssa_0 vec1 32 ssa_28 = ior ssa_27, ssa_26 vec1 32 ssa_29 = b32csel ssa_28, ssa_2, ssa_0 vec1 32 ssa_30 = ior ssa_19, ssa_29 vec1 64 ssa_31 = intrinsic load_uniform (ssa_6) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_32 = load_const (0x 2 /* 0.000000 */) vec1 64 ssa_33 = extract_u8 ssa_31, ssa_32 vec1 32 ssa_34 = unpack_64_2x32_split_x ssa_33 vec1 32 ssa_35 = unpack_64_2x32_split_y ssa_33 vec1 32 ssa_36 = load_const (0x000000f5 /* 0.000000 */) vec1 32 ssa_37 = ine32 ssa_34, ssa_36 vec1 32 ssa_38 = ine32 ssa_35, ssa_0 vec1 32 ssa_39 = ior ssa_38, ssa_37 vec1 32 ssa_40 = b32csel ssa_39, ssa_3, ssa_0 vec1 32 ssa_41 = ior ssa_30, ssa_40 vec1 32 ssa_42 = load_const (0x00000018 /* 0.000000 */) vec1 64 ssa_43 = intrinsic load_uniform (ssa_42) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_44 = load_const (0x 3 /* 0.000000 */) vec1 64 ssa_45 = extract_u8 ssa_43, ssa_44 vec1 32 ssa_46 = unpack_64_2x32_split_x ssa_45 vec1 32 ssa_47 = unpack_64_2x32_split_y ssa_45 vec1 32 ssa_48 = load_const (0x0000004f /* 0.000000 */) vec1 32 ssa_49 = ine32 ssa_46, ssa_48 vec1 32 ssa_50 = ine32 ssa_47, ssa_0 vec1 32 ssa_51 = ior ssa_50, ssa_49 vec1 32 ssa_52 = b32csel ssa_51, ssa_5, ssa_0 vec1 32 ssa_53 = ior ssa_41, ssa_52 vec1 64 ssa_54 = intrinsic load_uniform (ssa_4) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_55 = load_const (0x 4 /* 0.000000 */) vec1 64 ssa_56 = extract_u8 ssa_54, ssa_55 vec1 32 ssa_57 = unpack_64_2x32_split_x ssa_56 vec1 32 ssa_58 = unpack_64_2x32_split_y ssa_56 vec1 32 ssa_59 = load_const (0x00000073 /* 0.000000 */) vec1 32 ssa_60 = ine32 ssa_57, ssa_59 vec1 32 ssa_61 = ine32 ssa_58, ssa_0 vec1 32 ssa_62 = ior ssa_61, ssa_60 vec1 32 ssa_63 = b32csel ssa_62, ssa_6, ssa_0 vec1 32 ssa_64 = ior ssa_53, ssa_63 vec1 32 ssa_65 = load_const (0x00000028 /* 0.000000 */) vec1 64 ssa_66 = intrinsic load_uniform (ssa_65) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_67 = load_const (0x 5 /* 0.000000 */) vec1 64 ssa_68 = extract_u8 ssa_66, ssa_67 vec1 32 ssa_69 = unpack_64_2x32_split_x ssa_68 vec1 32 ssa_70 = unpack_64_2x32_split_y ssa_68 vec1 32 ssa_71 = load_const (0x00000027 /* 0.000000 */) vec1 32 ssa_72 = ine32 ssa_69, ssa_71 vec1 32 ssa_73 = ine32 ssa_70, ssa_0 vec1 32 ssa_74 = ior ssa_73, ssa_72 vec1 32 ssa_75 = b32csel ssa_74, ssa_4, ssa_0 vec1 32 ssa_76 = ior ssa_64, ssa_75 vec1 32 ssa_77 = load_const (0x00000030 /* 0.000000 */) vec1 64 ssa_78 = intrinsic load_uniform (ssa_77) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_79 = load_const (0x 6 /* 0.000000 */) vec1 64 ssa_80 = extract_u8 ssa_78, ssa_79 vec1 32 ssa_81 = unpack_64_2x32_split_x ssa_80 vec1 32 ssa_82 = unpack_64_2x32_split_y ssa_80 vec1 32 ssa_83 = load_const (0x0000002e /* 0.000000 */) vec1 32 ssa_84 = ine32 ssa_81, ssa_83 vec1 32 ssa_85 = ine32 ssa_82, ssa_0 vec1 32 ssa_86 = ior ssa_85, ssa_84 vec1 32 ssa_87 = b32csel ssa_86, ssa_7, ssa_0 vec1 32 ssa_88 = ior ssa_76, ssa_87 vec1 32 ssa_89 = load_const (0x00000038 /* 0.000000 */) vec1 64 ssa_90 = intrinsic load_uniform (ssa_89) (0, 64) /* base=0 */ /* range=64 */ /* ival */ vec1 64 ssa_91 = extract_u8 ssa_90, ssa_10 vec1 32 ssa_92 = unpack_64_2x32_split_x ssa_91 vec1 32 ssa_93 = unpack_64_2x32_split_y ssa_91 vec1 32 ssa_94 = ine32 ssa_92, ssa_25 vec1 32 ssa_95 = ine32 ssa_93, ssa_0 vec1 32 ssa_96 = ior ssa_95, ssa_94 vec1 32 ssa_97 = b32csel ssa_96, ssa_8, ssa_0 vec1 32 ssa_98 = ior ssa_88, ssa_97 vec1 32 ssa_99 = ieq32 ssa_98, ssa_0 /* succs: block_1 block_2 */ if ssa_99 { block block_1: /* preds: block_0 */ vec1 32 ssa_100 = load_const (0x3f800000 /* 1.000000 */) r2 = imov ssa_100 r1 = imov r2 r0 = imov ssa_0 /* succs: block_3 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_101 = u2f32 ssa_98 vec1 32 ssa_102 = load_const (0x3b808081 /* 0.003922 */) r0 = fmul ssa_101, ssa_102 vec1 32 ssa_104 = load_const (0x3f800000 /* 1.000000 */) r2 = imov ssa_104 r1 = imov ssa_0 /* succs: block_3 */ } block block_3: /* preds: block_1 block_2 */ vec4 32 ssa_108 = vec4 r0, r1, ssa_0, r2 intrinsic store_output (ssa_108, ssa_0) (8, 15, 0) /* base=8 */ /* wrmask=xyzw */ /* component=0 */ /* piglit_fragcolor */ /* succs: block_4 */ block block_4: } shader_runner: ../src/intel/compiler/brw_reg_type.c:208: brw_reg_type_to_hw_type: Assertion `devinfo->has_64bit_types || brw_reg_type_to_size(type) < 8 || type == BRW_REGISTER_TYPE_NF' failed. Aborted