diff --git a/src/i830_debug.c b/src/i830_debug.c index 8f8ef9b..b252c3f 100644 --- a/src/i830_debug.c +++ b/src/i830_debug.c @@ -192,6 +192,8 @@ DEBUGSTRING(i830_debug_dpll) p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> DPLL_FPA01_P1_POST_DIV_SHIFT); p2 = 14; + if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) + p2 = 7; } else { mode = "DAC/serial"; if (val & PLL_P1_DIVIDE_BY_TWO) { @@ -689,6 +691,19 @@ void i830DumpRegs (ScrnInfoPtr pScrn) xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "p1 out of range\n"); break; } + + switch ((dpll >> 13) & 0x3) { + case 0: + ref = 96000; + break; + case 3: + ref = 100000; + break; + default: + ref = 0; + xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "ref out of range\n"); + break; + } } else { @@ -726,18 +741,19 @@ void i830DumpRegs (ScrnInfoPtr pScrn) else p1 = ((dpll >> 16) & 0x3f) + 2; } - } - switch ((dpll >> 13) & 0x3) { - case 0: - ref = 96000; - break; - case 3: - ref = 100000; - break; - default: - ref = 0; - xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "ref out of range\n"); - break; + + switch ((dpll >> 13) & 0x3) { + case 0: + ref = 48000; + break; + case 3: + ref = 66000; + break; + default: + ref = 0; + xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "ref out of range\n"); + break; + } } if (IS_I965G(pI830)) { phase = (dpll >> 9) & 0xf; diff --git a/src/i830_display.c b/src/i830_display.c index d16871d..6a71bbb 100644 --- a/src/i830_display.c +++ b/src/i830_display.c @@ -1623,6 +1623,9 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, xf86CrtcPtr crtc) clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> DPLL_FPA01_P1_POST_DIV_SHIFT); clock.p2 = 14; + /* if LVDS is dual-channel, then p2 = 7 */ + if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) + clock.p2 = 7; if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) i8xx_clock(66000, &clock); /* XXX: might not be 66MHz */