From 46dfebeef38f20a6395d1e37c92ae5dd52e7c1dc Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Thu, 9 Nov 2017 16:59:49 -0800 Subject: [PATCH] intel/fs: Fix extract_(u|i)8 for 64-bit values on little-core --- src/intel/compiler/brw_fs_nir.cpp | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 15f2d88..535cc46 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1395,10 +1395,18 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) case nir_op_extract_u8: case nir_op_extract_i8: { - const brw_reg_type type = brw_int_type(1, instr->op == nir_op_extract_i8); nir_const_value *byte = nir_src_as_const_value(instr->src[1].src); assert(byte != NULL); - bld.MOV(result, subscript(op[0], type, byte->u32[0])); + if (nir_dest_bit_size(instr->dest.dest) == 64 && + (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) { + const unsigned shift = (type_sz(result.type) - byte->u32[0]) * 8; + bld.SHL(result, op[0], brw_imm_ud(shift)); + bld.SHR(result, result, brw_imm_ud(shift)); + } else { + const brw_reg_type type = + brw_int_type(1, instr->op == nir_op_extract_i8); + bld.MOV(result, subscript(op[0], type, byte->u32[0])); + } break; } -- 2.5.0.400.gff86faf