Subject: [PATCH] Add some misc debug logging for 12bpc issues

From: Tomeu Vizoso <[email-masked]>
Date: Mon, 13 Feb 2017 16:28:06 +0100

---
 drivers/gpu/drm/drm_edid.c           | 1 +
 drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
 drivers/gpu/drm/i915/intel_hdmi.c    | 1 +
 3 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 5a3b34a88ac3..5e54ae26cd1f 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3801,6 +3801,7 @@ static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
 	/* HDMI supports at least 8 bpc */
 	info->bpc = 8;
 
+	DRM_DEBUG_KMS("cea_db_payload_len(hdmi) %d info->bpc %d\n", cea_db_payload_len(hdmi), info->bpc);
 	if (cea_db_payload_len(hdmi) < 6)
 		return;
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 34c000859c0d..83ae2634ef32 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7520,6 +7520,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 		}
 	}
 
+	WARN_ON(pipe_config->pipe_bpp > 24);
+
 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
 		pipe_config->limited_color_range = true;
@@ -8052,6 +8054,9 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
 		BUG();
 	}
 
+	WARN_ON((val & PIPECONF_BPC_MASK) == PIPECONF_10BPC);
+	WARN_ON((val & PIPECONF_BPC_MASK) == PIPECONF_12BPC);
+
 	if (intel_crtc->config->dither)
 		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
 
@@ -8625,6 +8630,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 		break;
 	}
 
+	WARN_ON(pipe_config->pipe_bpp > 24);
+
 	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
 		pipe_config->limited_color_range = true;
 
@@ -11117,6 +11124,8 @@ connected_sink_compute_bpp(struct intel_connector *connector,
 		      connector->base.base.id,
 		      connector->base.name);
 
+	DRM_DEBUG_KMS("pipe_config->pipe_bpp %d info->bpc %d\n", pipe_config->pipe_bpp, info->bpc);
+
 	/* Don't use an invalid EDID bpc value */
 	if (info->bpc != 0 && info->bpc * 3 < bpp) {
 		DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index a580de80d2b5..53dd110ad461 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1355,6 +1355,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 	 * outputs. We also need to check that the higher clock still fits
 	 * within limits.
 	 */
+	DRM_DEBUG_KMS("pipe_config->pipe_bpp %d\n", pipe_config->pipe_bpp);
 	if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
 	    hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK &&
 	    hdmi_12bpc_possible(pipe_config)) {
-- 
2.9.3