Attachment 74737 Details for Bug 60391 – Disable WC PTE updates for ILK VTd

[patch] Disable WC PTE updates for ILK VTd

0001-drm-i915-Disable-WC-PTE-updates-to-w-a-buggy-IOMMU-o.patch (text/plain), 3.14 KB, created by Chris Wilson on 2013-02-13 09:28:13 UTC

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Creator: Chris Wilson

Created: 2013-02-13 09:28:13 UTC

Size: 3.14 KB

patch

obsolete

>From 360fbdbd2fb8ae7fbe6420ca7a87a1967b18817a Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Wed, 13 Feb 2013 09:20:48 +0000
>Subject: [PATCH] drm/i915: Disable WC PTE updates to w/a buggy IOMMU on ILK
>
>Whilst IOMMU is enabled for the Intel GPU on Ironlake, it appears that
>using WC writes to update the PTE on the GPU fail miserably. The result
>looks like the majority of the writes do not land leading to lots of
>screen corruption and a hard system hang.
>
>Reported-by: Nathan Myers <ncm@cantrip.org>
>Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=60391
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>Cc: stable@vger.kernel.org
>---
> drivers/char/agp/intel-gtt.c |   58 +++++++++++++++++++++++++++---------------
> 1 file changed, 37 insertions(+), 21 deletions(-)
>
>diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
>index dbd901e..ae953f4 100644
>--- a/drivers/char/agp/intel-gtt.c
>+++ b/drivers/char/agp/intel-gtt.c
>@@ -562,6 +562,41 @@ static void intel_gtt_cleanup(void)
> 	intel_gtt_teardown_scratch_page();
> }
> 
>+/* Certain Gen5 chipsets require require idling the GPU before
>+ * unmapping anything from the GTT when VT-d is enabled.
>+ */
>+static inline int needs_ilk_vtd_wa(void)
>+{
>+#ifdef CONFIG_INTEL_IOMMU
>+	const unsigned short gpu_devid = intel_private.pcidev->device;
>+
>+	/* Query intel_iommu to see if we need the workaround. Presumably that
>+	 * was loaded first.
>+	 */
>+	if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
>+	     gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
>+	     intel_iommu_gfx_mapped)
>+		return 1;
>+#endif
>+	return 0;
>+}
>+
>+
>+static bool intel_gtt_can_wc(void)
>+{
>+	if (INTEL_GTT_GEN <= 2)
>+		return false;
>+
>+	if (INTEL_GTT_GEN > 6)
>+		return false;
>+
>+	/* Reports of major corruption with ILK vt'd enabled */
>+	if (needs_ilk_vtd_wa())
>+		return false;
>+
>+	return true;
>+}
>+
> static int intel_gtt_init(void)
> {
> 	u32 gma_addr;
>@@ -591,7 +626,7 @@ static int intel_gtt_init(void)
> 	gtt_map_size = intel_private.base.gtt_total_entries * 4;
> 
> 	intel_private.gtt = NULL;
>-	if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2)
>+	if (intel_gtt_can_wc())
> 		intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
> 					       gtt_map_size);
> 	if (intel_private.gtt == NULL)
>@@ -1070,25 +1105,6 @@ static void i965_write_entry(dma_addr_t addr,
> 	writel(addr | pte_flags, intel_private.gtt + entry);
> }
> 
>-/* Certain Gen5 chipsets require require idling the GPU before
>- * unmapping anything from the GTT when VT-d is enabled.
>- */
>-static inline int needs_idle_maps(void)
>-{
>-#ifdef CONFIG_INTEL_IOMMU
>-	const unsigned short gpu_devid = intel_private.pcidev->device;
>-
>-	/* Query intel_iommu to see if we need the workaround. Presumably that
>-	 * was loaded first.
>-	 */
>-	if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
>-	     gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
>-	     intel_iommu_gfx_mapped)
>-		return 1;
>-#endif
>-	return 0;
>-}
>-
> static int i9xx_setup(void)
> {
> 	u32 reg_addr, gtt_addr;
>@@ -1116,7 +1132,7 @@ static int i9xx_setup(void)
> 		break;
> 	}
> 
>-	if (needs_idle_maps())
>+	if (needs_ilk_vtd_wa())
> 		intel_private.base.do_idle_maps = 1;
> 
> 	intel_i9xx_setup_flush();
>-- 
>1.7.10.4
>

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Attachments on bug 60391: 74664 | 74678 | 74713 | 74714 | 74737

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