Attachment 41400 Details for Bug 32606 – restore PLL selection, also save PLL0

[patch] restore PLL selection, also save PLL0

r128.diff (text/plain), 3.86 KB, created by Michael Lorenz on 2010-12-23 06:01:24 UTC

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Creator: Michael Lorenz

Created: 2010-12-23 06:01:24 UTC

Size: 3.86 KB

patch

obsolete

>Index: r128.h
>===================================================================
>RCS file: /cvsroot/xsrc/external/mit/xf86-video-r128/dist/src/r128.h,v
>retrieving revision 1.2
>retrieving revision 1.3
>diff -u -w -r1.2 -r1.3
>--- r128.h	10 Nov 2010 04:06:20 -0000	1.2
>+++ r128.h	23 Dec 2010 04:32:50 -0000	1.3
>@@ -71,6 +71,7 @@
> #define R128_MMIOSIZE  0x4000
> 
> #define R128_VBIOS_SIZE 0x00010000
>+#define R128_NAME "R128"
> 
> #if R128_DEBUG
> #define R128TRACE(x)                                          \
>@@ -169,6 +170,7 @@
> 				/* PLL registers */
>     CARD32     ppll_ref_div;
>     CARD32     ppll_div_3;
>+    CARD32     ppll_div_0;
>     CARD32     htotal_cntl;
> 
> 				/* Computed values for PLL2 */
>Index: r128_driver.c
>===================================================================
>RCS file: /cvsroot/xsrc/external/mit/xf86-video-r128/dist/src/r128_driver.c,v
>retrieving revision 1.2
>retrieving revision 1.3
>diff -u -w -r1.2 -r1.3
>--- r128_driver.c	10 Nov 2010 04:06:20 -0000	1.2
>+++ r128_driver.c	23 Dec 2010 04:32:50 -0000	1.3
>@@ -2871,6 +2871,15 @@
>     R128PLLWriteUpdate(pScrn);
>     R128PLLWaitForReadUpdateComplete(pScrn);
> 
>+    OUTPLLP(pScrn, R128_PPLL_DIV_0,
>+	    restore->ppll_div_0, ~R128_PPLL_FB0_DIV_MASK);
>+/*    R128PLLWriteUpdate(pScrn);*/
>+    OUTPLLP(pScrn, R128_PPLL_DIV_0,
>+	    restore->ppll_div_0, ~R128_PPLL_POST0_DIV_MASK);
>+
>+    R128PLLWriteUpdate(pScrn);
>+    R128PLLWaitForReadUpdateComplete(pScrn);
>+
>     OUTPLL(R128_HTOTAL_CNTL, restore->htotal_cntl);
> /*    R128PLLWriteUpdate(pScrn);*/
> 
>@@ -2952,11 +2961,7 @@
> 	       restore->p2pll_ref_div,
> 	       restore->p2pll_div_0,
> 	       restore->htotal_cntl2,
>-	       INPLL(pScrn, RADEON_P2PLL_CNTL)));
>-    R128TRACE(("Wrote: rd=%d, fd=%d, pd=%d\n",
>-	       restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
>-	       restore->p2pll_div_0 & RADEON_P2PLL_FB3_DIV_MASK,
>-	       (restore->p2pll_div_0 & RADEON_P2PLL_POST3_DIV_MASK) >>16));
>+	       INPLL(pScrn, R128_P2PLL_CNTL)));
> 
>     usleep(5000); /* Let the clock to lock */
> 
>@@ -3188,6 +3193,7 @@
> {
>     save->ppll_ref_div         = INPLL(pScrn, R128_PPLL_REF_DIV);
>     save->ppll_div_3           = INPLL(pScrn, R128_PPLL_DIV_3);
>+    save->ppll_div_0           = INPLL(pScrn, R128_PPLL_DIV_0);
>     save->htotal_cntl          = INPLL(pScrn, R128_HTOTAL_CNTL);
> 
>     R128TRACE(("Read: 0x%08x 0x%08x 0x%08x\n",
>@@ -3318,7 +3324,6 @@
>             vgaHWLock(hwp);
>         }
> #endif
>-
>         save->dp_datatype      = INREG(R128_DP_DATATYPE);
>         save->gen_reset_cntl   = INREG(R128_GEN_RESET_CNTL);
>         save->clock_cntl_index = INREG(R128_CLOCK_CNTL_INDEX);
>@@ -3355,6 +3360,15 @@
>     }
> 
>     R128RestoreMode(pScrn, restore);
>+
>+    if (!info->IsSecondary) {
>+        OUTREG(R128_AMCGPIO_MASK,     restore->amcgpio_mask);
>+        OUTREG(R128_AMCGPIO_EN_REG,   restore->amcgpio_en_reg);
>+        OUTREG(R128_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
>+        OUTREG(R128_GEN_RESET_CNTL,   restore->gen_reset_cntl);
>+        OUTREG(R128_DP_DATATYPE,      restore->dp_datatype);
>+    }
>+
> #ifdef WITH_VGAHW
>     if (info->VGAAccess) {
>         vgaHWPtr hwp = VGAHWPTR(pScrn);
>Index: r128_reg.h
>===================================================================
>RCS file: /cvsroot/xsrc/external/mit/xf86-video-r128/dist/src/r128_reg.h,v
>retrieving revision 1.1.1.1
>retrieving revision 1.2
>diff -u -w -r1.1.1.1 -r1.2
>--- r128_reg.h	12 Oct 2008 23:10:25 -0000	1.1.1.1
>+++ r128_reg.h	23 Dec 2010 04:32:50 -0000	1.2
>@@ -905,6 +905,8 @@
> #       define R128_PPLL_ATOMIC_UPDATE_EN     (1 << 16)
> #       define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
> #define R128_PPLL_DIV_0                   0x0004 /* PLL */
>+#       define R128_PPLL_FB0_DIV_MASK     0x07ff
>+#       define R128_PPLL_POST0_DIV_MASK   0x00070000
> #define R128_PPLL_DIV_1                   0x0005 /* PLL */
> #define R128_PPLL_DIV_2                   0x0006 /* PLL */
> #define R128_PPLL_DIV_3                   0x0007 /* PLL */

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