Attachment 30445 Details for Bug 24548 – Fix LVDS black screen issue after resuming from S3

[patch] Fix LVDS black screen issue after resuming from S3

arrandale-s3.patch (text/plain), 11.75 KB, created by minskey on 2009-10-15 02:33:47 UTC

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Creator: minskey

Created: 2009-10-15 02:33:47 UTC

Size: 11.75 KB

patch

obsolete

>diff -urp linux-2.6-vanilla/drivers/gpu/drm/i915/i915_drv.h linux-2.6-vanilla-patch/drivers/gpu/drm/i915/i915_drv.h
>--- linux-2.6-vanilla/drivers/gpu/drm/i915/i915_drv.h	2009-09-25 11:20:25.000000000 +0800
>+++ linux-2.6-vanilla-patch/drivers/gpu/drm/i915/i915_drv.h	2009-10-15 11:31:59.000000000 +0800
>@@ -305,6 +305,8 @@ typedef struct drm_i915_private {
> 	u32 savePFIT_PGM_RATIOS;
> 	u32 saveBLC_PWM_CTL;
> 	u32 saveBLC_PWM_CTL2;
>+	u32 saveBLC_CPU_PWM_CTL;
>+	u32 saveBLC_CPU_PWM_CTL2;
> 	u32 saveFPB0;
> 	u32 saveFPB1;
> 	u32 saveDPLL_B;
>@@ -348,6 +350,16 @@ typedef struct drm_i915_private {
> 	u32 saveIER;
> 	u32 saveIIR;
> 	u32 saveIMR;
>+	u32 saveDEIER;
>+	u32 saveDEIMR;
>+	u32 saveGTIER;
>+	u32 saveGTIMR;
>+	u32 savePFA_CTL_1;
>+	u32 savePFB_CTL_1;
>+	u32 saveFDI_RXA_CTL;
>+	u32 saveFDI_RXB_CTL;
>+	u32 saveFDI_RXA_IMR;
>+	u32 saveFDI_RXB_IMR;
> 	u32 saveCACHE_MODE_0;
> 	u32 saveD_STATE;
> 	u32 saveDSPCLK_GATE_D;
>diff -urp linux-2.6-vanilla/drivers/gpu/drm/i915/i915_suspend.c linux-2.6-vanilla-patch/drivers/gpu/drm/i915/i915_suspend.c
>--- linux-2.6-vanilla/drivers/gpu/drm/i915/i915_suspend.c	2009-09-25 11:20:25.000000000 +0800
>+++ linux-2.6-vanilla-patch/drivers/gpu/drm/i915/i915_suspend.c	2009-10-15 11:29:14.000000000 +0800
>@@ -32,11 +32,15 @@
> static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>+	u32	dpll_reg;
> 
>-	if (pipe == PIPE_A)
>-		return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
>-	else
>-		return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
>+	if (IS_IGDNG(dev)) {
>+		dpll_reg = (pipe == 0) ? PCH_DPLL_A: PCH_DPLL_B;
>+	} else {
>+		dpll_reg = (pipe == 0) ? DPLL_A: DPLL_B;
>+	}
>+
>+	return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
> }
> 
> static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
>@@ -232,9 +236,15 @@ static void i915_save_modeset_reg(struct
> 	/* Pipe & plane A info */
> 	dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
> 	dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
>-	dev_priv->saveFPA0 = I915_READ(FPA0);
>-	dev_priv->saveFPA1 = I915_READ(FPA1);
>-	dev_priv->saveDPLL_A = I915_READ(DPLL_A);
>+	if (IS_IGDNG(dev)) {
>+		dev_priv->saveFPA0 = I915_READ(PCH_FPA0);
>+		dev_priv->saveFPA1 = I915_READ(PCH_FPA1);
>+		dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A);
>+	} else {
>+		dev_priv->saveFPA0 = I915_READ(FPA0);
>+		dev_priv->saveFPA1 = I915_READ(FPA1);
>+		dev_priv->saveDPLL_A = I915_READ(DPLL_A);
>+	}
> 	if (IS_I965G(dev))
> 		dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
> 	dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
>@@ -260,9 +270,15 @@ static void i915_save_modeset_reg(struct
> 	/* Pipe & plane B info */
> 	dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
> 	dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
>-	dev_priv->saveFPB0 = I915_READ(FPB0);
>-	dev_priv->saveFPB1 = I915_READ(FPB1);
>-	dev_priv->saveDPLL_B = I915_READ(DPLL_B);
>+	if (IS_IGDNG(dev)) {
>+		dev_priv->saveFPB0 = I915_READ(PCH_FPB0);
>+		dev_priv->saveFPB1 = I915_READ(PCH_FPB1);
>+		dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B);
>+	} else {
>+		dev_priv->saveFPB0 = I915_READ(FPB0);
>+		dev_priv->saveFPB1 = I915_READ(FPB1);
>+		dev_priv->saveDPLL_B = I915_READ(DPLL_B);
>+	}
> 	if (IS_I965G(dev))
> 		dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
> 	dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
>@@ -271,7 +287,7 @@ static void i915_save_modeset_reg(struct
> 	dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
> 	dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
> 	dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
>-	dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
>+	dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
> 
> 	dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
> 	dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
>@@ -290,21 +306,39 @@ static void i915_save_modeset_reg(struct
> static void i915_restore_modeset_reg(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>+	int dpll_a_reg, fpa0_reg, fpa1_reg;
>+	int dpll_b_reg, fpb0_reg, fpb1_reg;
> 
> 	if (drm_core_check_feature(dev, DRIVER_MODESET))
> 		return;
> 
>+	if (IS_IGDNG(dev)) {
>+		dpll_a_reg = PCH_DPLL_A;
>+		dpll_b_reg = PCH_DPLL_B;
>+		fpa0_reg = PCH_FPA0;
>+		fpb0_reg = PCH_FPB0;
>+		fpa1_reg = PCH_FPA1;
>+		fpb1_reg = PCH_FPB1;
>+	} else {
>+		dpll_a_reg = DPLL_A;
>+		dpll_b_reg = DPLL_B;
>+		fpa0_reg = FPA0;
>+		fpb0_reg = FPB0;
>+		fpa1_reg = FPA1;
>+		fpb1_reg = FPB1;
>+	}
>+
> 	/* Pipe & plane A info */
> 	/* Prime the clock */
> 	if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
>-		I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
>+		I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
> 			   ~DPLL_VCO_ENABLE);
> 		DRM_UDELAY(150);
> 	}
>-	I915_WRITE(FPA0, dev_priv->saveFPA0);
>-	I915_WRITE(FPA1, dev_priv->saveFPA1);
>+	I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
>+	I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
> 	/* Actually enable it */
>-	I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
>+	I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
> 	DRM_UDELAY(150);
> 	if (IS_I965G(dev))
> 		I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
>@@ -339,14 +373,14 @@ static void i915_restore_modeset_reg(str
> 
> 	/* Pipe & plane B info */
> 	if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
>-		I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
>+		I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
> 			   ~DPLL_VCO_ENABLE);
> 		DRM_UDELAY(150);
> 	}
>-	I915_WRITE(FPB0, dev_priv->saveFPB0);
>-	I915_WRITE(FPB1, dev_priv->saveFPB1);
>+	I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
>+	I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
> 	/* Actually enable it */
>-	I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
>+	I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
> 	DRM_UDELAY(150);
> 	if (IS_I965G(dev))
> 		I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
>@@ -404,21 +438,45 @@ void i915_save_display(struct drm_device
> 		dev_priv->saveCURSIZE = I915_READ(CURSIZE);
> 
> 	/* CRT state */
>-	dev_priv->saveADPA = I915_READ(ADPA);
>+	if (IS_IGDNG(dev)) {
>+		dev_priv->saveADPA = I915_READ(PCH_ADPA);
>+	} else {
>+		dev_priv->saveADPA = I915_READ(ADPA);
>+	}
> 
> 	/* LVDS state */
>-	dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
>-	dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
>-	dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
>-	if (IS_I965G(dev))
>-		dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
>-	if (IS_MOBILE(dev) && !IS_I830(dev))
>-		dev_priv->saveLVDS = I915_READ(LVDS);
>+	if (IS_IGDNG(dev)) {
>+		dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
>+		dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
>+		dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
>+		dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
>+		dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
>+		dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
>+		dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1);
>+		dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1);
>+		dev_priv->saveLVDS = I915_READ(PCH_LVDS);
>+	} else {
>+		dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
>+		dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
>+		dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
>+		if (IS_I965G(dev))
>+			dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
>+	 	if (IS_MOBILE(dev) && !IS_I830(dev))
>+			dev_priv->saveLVDS = I915_READ(LVDS);
>+	}
>+
> 	if (!IS_I830(dev) && !IS_845G(dev))
> 		dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
>-	dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
>-	dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
>-	dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
>+	
>+	if (IS_IGDNG(dev)) {
>+		dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
>+		dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
>+		dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
>+	} else {
>+		dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
>+		dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
>+		dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
>+	}
> 
> 	/* Display Port state */
> 	if (SUPPORTS_INTEGRATED_DP(dev)) {
>@@ -446,7 +504,10 @@ void i915_save_display(struct drm_device
> 	dev_priv->saveVGA0 = I915_READ(VGA0);
> 	dev_priv->saveVGA1 = I915_READ(VGA1);
> 	dev_priv->saveVGA_PD = I915_READ(VGA_PD);
>-	dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
>+	if (IS_IGDNG(dev))
>+		dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
>+	else
>+		dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
> 
> 	i915_save_vga(dev);
> }
>@@ -485,22 +546,43 @@ void i915_restore_display(struct drm_dev
> 		I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
> 
> 	/* CRT state */
>-	I915_WRITE(ADPA, dev_priv->saveADPA);
>+	if (IS_IGDNG(dev))
>+		I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
>+	else
>+		I915_WRITE(ADPA, dev_priv->saveADPA);
> 
> 	/* LVDS state */
>-	if (IS_I965G(dev))
>+	if (IS_I965G(dev) && !IS_IGDNG(dev))
> 		I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
>-	if (IS_MOBILE(dev) && !IS_I830(dev))
>+
>+	if (IS_IGDNG(dev)) {
>+		I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
>+	} else if (IS_MOBILE(dev) && !IS_I830(dev))
> 		I915_WRITE(LVDS, dev_priv->saveLVDS);
>+
> 	if (!IS_I830(dev) && !IS_845G(dev))
> 		I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
> 
> 	I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
>-	I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
>-	I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
>-	I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
>-	I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
>-	I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
>+	if (IS_IGDNG(dev)) {
>+		I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
>+		I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
>+		I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
>+		I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
>+		I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1);
>+		I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1);
>+		I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
>+		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
>+		I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
>+		I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
>+	}
>+	else {
>+		I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
>+		I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
>+		I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
>+		I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
>+		I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
>+	}
> 
> 	/* Display Port state */
> 	if (SUPPORTS_INTEGRATED_DP(dev)) {
>@@ -517,7 +599,10 @@ void i915_restore_display(struct drm_dev
> 	I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
> 
> 	/* VGA state */
>-	I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
>+	if (IS_IGDNG(dev))
>+		 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
>+	else
>+		I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
> 	I915_WRITE(VGA0, dev_priv->saveVGA0);
> 	I915_WRITE(VGA1, dev_priv->saveVGA1);
> 	I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
>@@ -543,8 +628,17 @@ int i915_save_state(struct drm_device *d
> 	i915_save_display(dev);
> 
> 	/* Interrupt state */
>-	dev_priv->saveIER = I915_READ(IER);
>-	dev_priv->saveIMR = I915_READ(IMR);
>+	if (IS_IGDNG(dev)) {
>+		dev_priv->saveDEIER = I915_READ(DEIER);
>+		dev_priv->saveDEIMR = I915_READ(DEIMR);
>+		dev_priv->saveGTIER = I915_READ(GTIER);
>+		dev_priv->saveGTIMR = I915_READ(GTIMR);
>+		dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
>+		dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
>+	} else {
>+		dev_priv->saveIER = I915_READ(IER);
>+		dev_priv->saveIMR = I915_READ(IMR);
>+	}
> 
> 	/* Clock gating state */
> 	dev_priv->saveD_STATE = I915_READ(D_STATE);
>@@ -609,8 +703,17 @@ int i915_restore_state(struct drm_device
> 	i915_restore_display(dev);
> 
> 	/* Interrupt state */
>-	I915_WRITE (IER, dev_priv->saveIER);
>-	I915_WRITE (IMR,  dev_priv->saveIMR);
>+	 if (IS_IGDNG(dev)) {
>+		I915_WRITE(DEIER, dev_priv->saveDEIER);
>+		I915_WRITE(DEIMR, dev_priv->saveDEIMR);
>+		I915_WRITE(GTIER, dev_priv->saveGTIER);
>+		I915_WRITE(GTIMR, dev_priv->saveGTIMR);
>+		I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
>+		I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
>+	} else {
>+		I915_WRITE (IER, dev_priv->saveIER);
>+		I915_WRITE (IMR,  dev_priv->saveIMR);
>+	}
> 
> 	/* Clock gating state */
> 	I915_WRITE (D_STATE, dev_priv->saveD_STATE);

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