Attachment 29932 Details for Bug 24021 – reg_dumper on the Dell Latitude E5500

reg_dumper on the Dell Latitude E5500

reg_dumper (text/plain), 11.87 KB, created by Damien Lallement on 2009-09-29 02:02:20 UTC

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Creator: Damien Lallement

Created: 2009-09-29 02:02:20 UTC

Size: 11.87 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):                  DCC: 0x000f0400 (single or dual channel asymmetric, XOR randomization: disabled, XOR bit: 11)
>(II):            CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>(II):               C0DRB0: 0x000f0400 (0x0400)
>(II):               C0DRB1: 0x0000000f (0x000f)
>(II):               C0DRB2: 0x00000000 (0x0000)
>(II):               C0DRB3: 0x00e00000 (0x0000)
>(II):               C1DRB0: 0x00000000 (0x0000)
>(II):               C1DRB1: 0x00000000 (0x0000)
>(II):               C1DRB2: 0x00000000 (0x0000)
>(II):               C1DRB3: 0x00000000 (0x0000)
>(II):              C0DRA01: 0x000300e0 (0x00e0)
>(II):              C0DRA23: 0x001c0003 (0x0003)
>(II):              C1DRA01: 0x00000000 (0x0000)
>(II):              C1DRA23: 0x00000000 (0x0000)
>(II):           PGETBL_CTL: 0x00000001
>(II):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II):            DPLL_TEST: 0x00010001 ()
>(II):         CACHE_MODE_0: 0x00006820
>(II):              D_STATE: 0x00000000
>(II):        DSPCLK_GATE_D: 0x1004000c (clock gates disabled: VRHUNIT DSSUNIT OVRUNIT OVCUNIT)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x000002c0
>(II):                SDVOB: 0x0000001c (disabled, pipe A, stall disabled, detected)
>(II):                SDVOC: 0x0000001c (disabled, pipe A, stall disabled, detected)
>(II):              SDVOUDI: 0x00000000
>(II):               DSPARB: 0x00000000
>(II):               DSPFW1: 0x3f8f0f0f
>(II):               DSPFW2: 0x150f0f0f
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
>(II):                 LVDS: 0xc2208300 (enabled, pipe B, 18 bit, 1 channel)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x0000001c (disabled, pipe A, no stall, +hsync, +vsync)
>(II):                 DVOC: 0x0000001c (disabled, pipe A, no stall, +hsync, +vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000001 (power target: on)
>(II):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x01f408fc
>(II):        PP_OFF_DELAYS: 0x019008fc
>(II):           PP_DIVISOR: 0x003e7f06
>(II):         PFIT_CONTROL: 0x00000000
>(II):      PFIT_PGM_RATIOS: 0x0c000a00
>(II):      PORT_HOTPLUG_EN: 0x3e040320
>(II):    PORT_HOTPLUG_STAT: 0x08000000
>(II):             DSPACNTR: 0x58000000 (disabled, pipe A)
>(II):           DSPASTRIDE: 0x00001400 (5120 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x00000000 (1, 1)
>(II):             DSPABASE: 0x00000000
>(II):             DSPASURF: 0x02446000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x00000000 (disabled, inactive)
>(II):             PIPEASRC: 0x04ff03ff (1280, 1024)
>(II):            PIPEASTAT: 0x00040000 (status: SVBLANK_INT_ENABLE)
>(II):    PIPEA_GMCH_DATA_M: 0x00000000
>(II):    PIPEA_GMCH_DATA_N: 0x00000000
>(II):      PIPEA_DP_LINK_M: 0x00000000
>(II):      PIPEA_DP_LINK_N: 0x00000000
>(II):        CURSOR_A_BASE: 0x02420000
>(II):     CURSOR_A_CONTROL: 0x00000000
>(II):    CURSOR_A_POSITION: 0x00000000
>(II):                 FPA0: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
>(II):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_A: 0x14020003 (disabled, non-dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x06af04ff (1280 active, 1712 total)
>(II):             HBLANK_A: 0x06af04ff (1280 start, 1712 end)
>(II):              HSYNC_A: 0x05d70557 (1368 start, 1496 end)
>(II):             VTOTAL_A: 0x044f03ff (1024 active, 1104 total)
>(II):             VBLANK_A: 0x044f03ff (1024 start, 1104 end)
>(II):              VSYNC_A: 0x04090402 (1027 start, 1034 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000400 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00001400 (5120 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x00000000 (1, 1)
>(II):             DSPBBASE: 0x00000000
>(II):             DSPBSURF: 0x02020000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0xc0000000 (enabled, active)
>(II):             PIPEBSRC: 0x04ff031f (1280, 800)
>(II):            PIPEBSTAT: 0x00400206 (status: LBLC_EVENT_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>(II):    PIPEB_GMCH_DATA_M: 0x00000000
>(II):    PIPEB_GMCH_DATA_N: 0x00000000
>(II):      PIPEB_DP_LINK_M: 0x00000000
>(II):      PIPEB_DP_LINK_N: 0x00000000
>(II):        CURSOR_B_BASE: 0x02425000
>(II):     CURSOR_B_CONTROL: 0x10000000
>(II):    CURSOR_B_POSITION: 0x0080039e
>(II):                 FPB0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_B: 0x98046000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 3, p2 = 14)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x055004ff (1280 active, 1361 total)
>(II):             HBLANK_B: 0x055004ff (1280 start, 1361 end)
>(II):              HSYNC_B: 0x054f052f (1328 start, 1360 end)
>(II):             VTOTAL_B: 0x0329031f (800 active, 810 total)
>(II):             VBLANK_B: 0x0329031f (800 start, 810 end)
>(II):              VSYNC_B: 0x03280322 (803 start, 809 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00031108
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x00020002
>(II):             VGACNTRL: 0xa2c4008e (disabled)
>(II):               TV_CTL: 0x000c0000
>(II):               TV_DAC: 0x70000000
>(II):             TV_CSC_Y: 0x0332012d
>(II):            TV_CSC_Y2: 0x07d30104
>(II):             TV_CSC_U: 0x0733052d
>(II):            TV_CSC_U2: 0x05c70200
>(II):             TV_CSC_V: 0x0340030c
>(II):            TV_CSC_V2: 0x06d00200
>(II):         TV_CLR_KNOBS: 0x00000000
>(II):         TV_CLR_LEVEL: 0x010b00e1
>(II):           TV_H_CTL_1: 0x00400359
>(II):           TV_H_CTL_2: 0x80480022
>(II):           TV_H_CTL_3: 0x007c0344
>(II):           TV_V_CTL_1: 0x00f01415
>(II):           TV_V_CTL_2: 0x00060607
>(II):           TV_V_CTL_3: 0x80120001
>(II):           TV_V_CTL_4: 0x000900f0
>(II):           TV_V_CTL_5: 0x000a00f0
>(II):           TV_V_CTL_6: 0x000900f0
>(II):           TV_V_CTL_7: 0x000a00f0
>(II):          TV_SC_CTL_1: 0xc1710087
>(II):          TV_SC_CTL_2: 0x6b405140
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00360024
>(II):          TV_WIN_SIZE: 0x02640198
>(II):      TV_FILTER_CTL_1: 0x8000085e
>(II):      TV_FILTER_CTL_2: 0x00028283
>(II):      TV_FILTER_CTL_3: 0x00014141
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0xb1403000
>(II):         TV_H_LUMA_59: 0x0000b060
>(II):        TV_H_CHROMA_0: 0xb1403000
>(II):       TV_H_CHROMA_59: 0x0000b060
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x7fff87ff
>(II):          FBC_COMMAND: 0x08c80032
>(II):           FBC_STATUS: 0x00000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0xe300a900
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000200
>(II):         MI_ARB_STATE: 0x00000040
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x0000001c
>(II):       DPB_AUX_CH_CTL: 0x00050000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x0000001c
>(II):       DPC_AUX_CH_CTL: 0x00050000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x0000001c
>(II):       DPD_AUX_CH_CTL: 0x00050000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II):           AUD_CONFIG: 0x00000004
>(II):     AUD_HDMIW_STATUS: 0x00000000
>(II):       AUD_CONV_CHCNT: 0x00000000
>(II):        VIDEO_DIP_CTL: 0x20000600
>(II):        AUD_PINW_CNTR: 0x00000140
>(II):          AUD_CNTL_ST: 0x00002000
>(II):          AUD_PIN_CAP: 0x00000094
>(II):         AUD_PINW_CAP: 0x004073bd
>(II):   AUD_PINW_UNSOLRESP: 0x00000000
>(II):     AUD_OUT_DIG_CNVT: 0x00000001
>(II):        AUD_OUT_CWCAP: 0x00006211
>(II):          AUD_GRP_CAP: 0x00000004
>(II):        FENCE START 0: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 0: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 1: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 1: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 2: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 2: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 3: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 3: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 4: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 4: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 5: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 5: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 6: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 6: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 7: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 7: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 8: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 8: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 9: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 9: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 10: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 10: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 11: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 11: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 12: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 12: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 13: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 13: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 14: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 14: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 15: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 15: 0x00000000 (                                   0x00000000 end)
>(II): SDVO phase shift 0 out of range -- probobly not an issue.
>(II): pipe A dot 108000 n 2 m1 14 m2 8 p1 2 p2 10
>(II): SDVO phase shift 0 out of range -- probobly not an issue.
>(II): pipe B dot 64880 n 2 m1 18 m2 7 p1 3 p2 14
>(II): DumpRegsEnd

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Attachments on bug 24021: 29836 | 29918 | 29932 | 29934 | 29935 | 29936 | 30616 | 30624 | 31885

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