Attachment 27574 Details for Bug 22702 – reg_dumper with 2.7.1 / works fine

reg_dumper with 2.7.1 / works fine

reg_dumper-stable.txt (text/plain), 11.01 KB, created by Hanno Böck on 2009-07-10 10:52:35 UTC

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Creator: Hanno Böck

Created: 2009-07-10 10:52:35 UTC

Size: 11.01 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):                  DCC: 0x000f0400 (single or dual channel asymmetric, XOR randomization: disabled, XOR bit: 11)
>(II):            CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>(II):               C0DRB0: 0x000f0400 (0x0400)
>(II):               C0DRB1: 0x0010000f (0x000f)
>(II):               C0DRB2: 0x00000010 (0x0010)
>(II):               C0DRB3: 0x0e000000 (0x0000)
>(II):               C1DRB0: 0x17cbe000 (0xe000)
>(II):               C1DRB1: 0x000017cb (0x17cb)
>(II):               C1DRB2: 0x00000000 (0x0000)
>(II):               C1DRB3: 0x00000000 (0x0000)
>(II):              C0DRA01: 0x00030e00 (0x0e00)
>(II):              C0DRA23: 0x000c0003 (0x0003)
>(II):              C1DRA01: 0x00000000 (0x0000)
>(II):              C1DRA23: 0x00000000 (0x0000)
>(II):           PGETBL_CTL: 0x7ef80001
>(II):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II):            DPLL_TEST: 0x00010001 ()
>(II):         CACHE_MODE_0: 0x00006800
>(II):              D_STATE: 0x00000000
>(II):        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0x0008001c (disabled, pipe A, stall disabled, detected)
>(II):                SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>(II):              SDVOUDI: 0x00000000
>(II):               DSPARB: 0x00001d9c
>(II):               DSPFW1: 0x3f8f0f0f
>(II):               DSPFW2: 0x00000f0f
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0xc0008c18 (enabled, pipe B, +hsync, +vsync)
>(II):                 LVDS: 0xc230833c (enabled, pipe B, 18 bit, 2 channels)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x0008001c (disabled, pipe A, no stall, +hsync, +vsync)
>(II):                 DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000003 (power target: on)
>(II):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x00fa09c4
>(II):        PP_OFF_DELAYS: 0x00fa09c4
>(II):           PP_DIVISOR: 0x00410903
>(II):         PFIT_CONTROL: 0x00000000
>(II):      PFIT_PGM_RATIOS: 0x06180750
>(II):      PORT_HOTPLUG_EN: 0x06040220
>(II):    PORT_HOTPLUG_STAT: 0x00000000
>(II):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x00000000 (1, 1)
>(II):             DSPABASE: 0x00000000
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x00000000 (disabled, inactive)
>(II):             PIPEASRC: 0x027f01df (640, 480)
>(II):            PIPEASTAT: 0x00000000 (status:)
>(II):    PIPEA_GMCH_DATA_M: 0x00000000
>(II):    PIPEA_GMCH_DATA_N: 0x00000000
>(II):      PIPEA_DP_LINK_M: 0x00000000
>(II):      PIPEA_DP_LINK_N: 0x00000000
>(II):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_A: 0x04800c00 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II):            DPLL_A_MD: 0x00000303
>(II):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000400 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00001600 (5632 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x00000000 (1, 1)
>(II):             DSPBBASE: 0x00000000
>(II):             DSPBSURF: 0x00d93000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0xc0000000 (enabled, active)
>(II):             PIPEBSRC: 0x05770419 (1400, 1050)
>(II):            PIPEBSTAT: 0x00400206 (status: LBLC_EVENT_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>(II):    PIPEB_GMCH_DATA_M: 0x00000000
>(II):    PIPEB_GMCH_DATA_N: 0x00000000
>(II):      PIPEB_DP_LINK_M: 0x00000000
>(II):      PIPEB_DP_LINK_N: 0x00000000
>(II):                 FPB0: 0x00051109 (n = 5, m1 = 17, m2 = 9)
>(II):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_B: 0x99026c00 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 2, p2 = 7)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x06970577 (1400 active, 1688 total)
>(II):             HBLANK_B: 0x06970577 (1400 start, 1688 end)
>(II):              HSYNC_B: 0x061705a7 (1448 start, 1560 end)
>(II):             VTOTAL_B: 0x04290419 (1050 active, 1066 total)
>(II):             VBLANK_B: 0x04290419 (1050 start, 1066 end)
>(II):              VSYNC_B: 0x041d041a (1051 start, 1054 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00031108
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x00020002
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x00000000
>(II):               TV_DAC: 0x70000000
>(II):             TV_CSC_Y: 0x00000000
>(II):            TV_CSC_Y2: 0x00000000
>(II):             TV_CSC_U: 0x00000000
>(II):            TV_CSC_U2: 0x00000000
>(II):             TV_CSC_V: 0x00000000
>(II):            TV_CSC_V2: 0x00000000
>(II):         TV_CLR_KNOBS: 0x00000000
>(II):         TV_CLR_LEVEL: 0x00000000
>(II):           TV_H_CTL_1: 0x00000000
>(II):           TV_H_CTL_2: 0x00000000
>(II):           TV_H_CTL_3: 0x00000000
>(II):           TV_V_CTL_1: 0x00000000
>(II):           TV_V_CTL_2: 0x00000000
>(II):           TV_V_CTL_3: 0x00000000
>(II):           TV_V_CTL_4: 0x00000000
>(II):           TV_V_CTL_5: 0x00000000
>(II):           TV_V_CTL_6: 0x00000000
>(II):           TV_V_CTL_7: 0x00000000
>(II):          TV_SC_CTL_1: 0x00000000
>(II):          TV_SC_CTL_2: 0x00000000
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00000000
>(II):          TV_WIN_SIZE: 0x00000000
>(II):      TV_FILTER_CTL_1: 0x00000000
>(II):      TV_FILTER_CTL_2: 0x00000000
>(II):      TV_FILTER_CTL_3: 0x00000000
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0x00000000
>(II):         TV_H_LUMA_59: 0x00000000
>(II):        TV_H_CHROMA_0: 0x00000000
>(II):       TV_H_CHROMA_59: 0x00000000
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x00000000
>(II):          FBC_COMMAND: 0x00000000
>(II):           FBC_STATUS: 0x20000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0x00000000
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000200
>(II):         MI_ARB_STATE: 0x00000044
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000000
>(II):       DPB_AUX_CH_CTL: 0x00000000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000000
>(II):       DPC_AUX_CH_CTL: 0x00000000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x00000000
>(II):       DPD_AUX_CH_CTL: 0x00000000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II):        FENCE START 0: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 0: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 1: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 1: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 2: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 2: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 3: 0x00d930ad ( enabled, X tile walk, 5504 pitch, 0x00d93000 start)
>(II):          FENCE END 3: 0x01592000 (                                   0x01592000 end)
>(II):        FENCE START 4: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 4: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 5: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 5: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 6: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 6: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 7: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 7: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 8: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 8: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 9: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 9: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 10: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 10: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 11: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 11: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 12: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 12: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 13: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 13: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 14: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 14: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 15: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 15: 0x00000000 (                                   0x00000000 end)
>(II): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II): pipe B dot 108163 n 5 m1 17 m2 9 p1 2 p2 7
>(II): DumpRegsEnd

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Attachments on bug 22702: 27572 | 27573 | 27574

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