Attachment 26282 Details for Bug 21986 – log file

log file

Xorg.0.log.old (text/plain), 107.14 KB, created by Oswald Buddenhagen on 2009-05-28 13:07:23 UTC

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Creator: Oswald Buddenhagen

Created: 2009-05-28 13:07:23 UTC

Size: 107.14 KB

patch

obsolete

>
>This is a pre-release version of the X server from The X.Org Foundation.
>It is not supported in any way.
>Bugs may be filed in the bugzilla at http://bugs.freedesktop.org/.
>Select the "xorg" product for bugs you find in this release.
>Before reporting bugs in pre-release versions please check the
>latest version in the X.Org Foundation git repository.
>See http://wiki.x.org/wiki/GitPage for git access instructions.
>
>X.Org X Server 1.6.99.1
>Release Date: (unreleased)
>X Protocol Version 11, Revision 0
>Build Operating System: Linux 2.6.29.4 i686 
>Current Operating System: Linux ugly.local 2.6.29.4 #17 PREEMPT Tue May 19 21:37:29 CEST 2009 i686
>Build Date: 23 May 2009  11:33:25PM
> 
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/opt/xorg/var/log/Xorg.0.log", Time: Thu May 28 21:51:42 2009
>(==) Using config file: "/etc/X11/xorg.conf"
>(==) ServerLayout "Simple Layout"
>(**) |-->Screen "onboard" (0)
>(**) |   |-->Monitor "19-zoller"
>(**) |   |-->Device "onboard"
>(**) |-->Input Device "MS3"
>(**) |-->Input Device "Keyboard1"
>(**) Option "DontZap" "false"
>(**) Option "AllowEmptyInput" "false"
>(==) Automatically adding devices
>(==) Automatically enabling devices
>(WW) The directory "/opt/xorg/lib/X11/fonts/misc/" does not exist.
>	Entry deleted from font path.
>(WW) The directory "/opt/xorg/lib/X11/fonts/TTF/" does not exist.
>	Entry deleted from font path.
>(WW) The directory "/opt/xorg/lib/X11/fonts/OTF" does not exist.
>	Entry deleted from font path.
>(WW) The directory "/opt/xorg/lib/X11/fonts/Type1/" does not exist.
>	Entry deleted from font path.
>(WW) The directory "/opt/xorg/lib/X11/fonts/100dpi/" does not exist.
>	Entry deleted from font path.
>(WW) The directory "/opt/xorg/lib/X11/fonts/75dpi/" does not exist.
>	Entry deleted from font path.
>(**) FontPath set to:
>	/usr/share/fonts/X11/lfp-fix:unscaled,
>	/usr/share/fonts/X11/75dpi:unscaled,
>	/usr/share/fonts/X11/100dpi:unscaled,
>	/usr/share/fonts/X11/misc:unscaled,
>	/usr/share/fonts/X11/ossi:unscaled,
>	/usr/share/fonts/X11/Type1,
>	/usr/share/fonts/X11/75dpi,
>	/usr/share/fonts/X11/100dpi,
>	/usr/share/fonts/X11/misc,
>	/usr/share/fonts/X11/ossi,
>	built-ins
>(==) ModulePath set to "/opt/xorg/lib/xorg/modules"
>(**) Extension "Composite" is disabled
>(II) Loader magic: 0x819a898
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.4
>	X.Org Video Driver: 5.0
>	X.Org XInput driver : 5.0
>	X.Org Server Extension : 2.0
>(++) using VT number 7
>
>(--) PCI:*(0@0:2:0) unknown vendor (0x8086) unknown chipset (0x2562) rev 3, Mem @ 0xf0000000/134217728, 0xef000000/524288
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) System resource ranges:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>(II) "extmod" will be loaded by default.
>(II) "dbe" will be loaded by default.
>(II) "glx" will be loaded by default.
>(II) "dri" will be loaded by default.
>(II) "dri2" will be loaded by default.
>(II) LoadModule: "extmod"
>(II) Loading /opt/xorg/lib/xorg/modules/extensions/libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "dbe"
>(II) Loading /opt/xorg/lib/xorg/modules/extensions/libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "glx"
>(II) Loading /opt/xorg/lib/xorg/modules/extensions/libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(==) AIGLX enabled
>(II) Loading extension GLX
>(II) LoadModule: "dri"
>(II) Loading /opt/xorg/lib/xorg/modules/extensions/libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "dri2"
>(II) Loading /opt/xorg/lib/xorg/modules/extensions/libdri2.so
>(II) Module dri2: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.1.0
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension DRI2
>(II) LoadModule: "intel"
>(II) Loading /opt/xorg/lib/xorg/modules/drivers/intel_drv.so
>(II) Module intel: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 2.7.99
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 5.0
>(II) LoadModule: "mouse"
>(II) Loading /opt/xorg/lib/xorg/modules/input/mouse_drv.so
>(II) Module mouse: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.4.0
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 5.0
>(II) LoadModule: "kbd"
>(II) Loading /opt/xorg/lib/xorg/modules/input/kbd_drv.so
>(II) Module kbd: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.3.2
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 5.0
>(II) intel: Driver for Intel Integrated Graphics Chipsets: i810,
>	i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G,
>	E7221 (i915), 915GM, 945G, 945GM, 945GME, IGD_GM, IGD_G, 965G, G35,
>	965Q, 946GZ, 965GM, 965GME/GLE, G33, Q35, Q33,
>	Mobile IntelÂ® GM45 Express Chipset,
>	Intel Integrated Graphics Device, G45/G43, Q45/Q43, G41
>(II) Primary Device is: PCI 00@00:02:0
>(II) resource ranges after xf86ClaimFixedResources() call:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>(II) resource ranges after probing:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B]
>	[5] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B]
>	[6] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B]
>	[7] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[8] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>	[9] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B]
>	[10] 0	0	0x000003c0 - 0x000003df (0x20) IS[B]
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>(II) Loading /opt/xorg/lib/xorg/modules/libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 5.0
>(II) Loading sub module "ramdac"
>(II) LoadModule: "ramdac"
>(II) Module "ramdac" already built-in
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 8, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 8, (OK)
>drmOpenByBusid: drmOpenMinor returns 8
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(**) intel(0): Depth 24, (--) framebuffer bpp 32
>(==) intel(0): RGB weight 888
>(==) intel(0): Default visual is TrueColor
>(**) intel(0): Option "DRI" "no"
>(**) intel(0): Option "ModeDebug" "true"
>(II) intel(0): Integrated Graphics Chipset: Intel(R) 845G
>(--) intel(0): Chipset: "845G"
>(--) intel(0): Linear framebuffer at 0xF0000000
>(--) intel(0): IO registers at addr 0xEF000000
>(WW) intel(0): libpciaccess reported 0 rom size, guessing 64kB
>(--) intel(0): Using UXA for acceleration
>(II) intel(0): Hardware state on X startup:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x6ff000ef (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep present)
>(II) intel(0):               C0DRB0: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB1: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB0: 0xbb2c511a (0x511a)
>(II) intel(0):               C1DRB1: 0x694cbb2c (0xbb2c)
>(II) intel(0):               C1DRB2: 0x6f4c694c (0x694c)
>(II) intel(0):               C1DRB3: 0x00066f4c (0x6f4c)
>(II) intel(0):              C0DRA01: 0x00000000 (0x0000)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x01560006 (0x0006)
>(II) intel(0):              C1DRA23: 0x03810156 (0x0156)
>(II) intel(0):           PGETBL_CTL: 0x3ffe0001
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4)
>(II) intel(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) intel(0):         CACHE_MODE_0: 0x00000000
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x0000005f
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80008000 (enabled, pipe A, -hsync, -vsync)
>(II) intel(0):                 LVDS: 0x0000b001 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x1408c080
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x00000000 (1, 1)
>(II) intel(0):            PIPEASTAT: 0x80000207 (status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):    PIPEA_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEA_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):               DPLL_A: 0x808b0000 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 13, p2 = 4)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x00000000 (1, 1)
>(II) intel(0):            PIPEBSTAT: 0x00000000 (status:)
>(II) intel(0):    PIPEB_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEB_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):                 FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):               DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             HBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              HSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):             VTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             VBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              VSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b
>(II) intel(0):             VGACNTRL: 0x0020008e (enabled)
>(II) intel(0):               TV_CTL: 0x031f027f
>(II) intel(0):               TV_DAC: 0x03170287
>(II) intel(0):             TV_CSC_Y: 0x020401e7
>(II) intel(0):            TV_CSC_Y2: 0x01eb01e9
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00130000
>(II) intel(0):          TV_SC_CTL_2: 0x00380400
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x031f027f
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x00000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000000
>(II) intel(0):         MI_ARB_STATE: 0x00000000
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x031f027f
>(II) intel(0):       DPC_AUX_CH_CTL: 0x020401e7
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x01eb01e9
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):             FENCE  0: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  3: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  4: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0): pipe A dot 25153 n 2 m1 18 m2 7 p1 13 p2 4
>(II) intel(0): pipe B dot 72000 n 0 m1 0 m2 0 p1 2 p2 2
>(II) intel(0): DumpRegsEnd
>(II) intel(0): 1 display pipe available.
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"
>(II) Module "ddc" already built-in
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"
>(II) Module "i2c" already built-in
>(II) intel(0): Output VGA using monitor section 19-zoller
>(II) intel(0): I2C bus "DVODDC_D" initialized.
>(II) Loading sub module "sil164"
>(II) LoadModule: "sil164"
>(II) Loading /opt/xorg/lib/xorg/modules/drivers/sil164.so
>(II) Module sil164: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 5.0
>(II) intel(0): I2C bus "DVOI2C_E" initialized.
>(II) Loading sub module "ch7xxx"
>(II) LoadModule: "ch7xxx"
>(II) Loading /opt/xorg/lib/xorg/modules/drivers/ch7xxx.so
>(II) Module ch7xxx: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 5.0
>(II) intel(0): I2C bus "DVOI2C_E" removed.
>(II) intel(0): I2C bus "DVOI2C_E" initialized.
>(II) Loading sub module "ivch"
>(II) LoadModule: "ivch"
>(II) Loading /opt/xorg/lib/xorg/modules/drivers/ivch.so
>(II) Module ivch: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 5.0
>(II) intel(0): I2C bus "DVOI2C_E" removed.
>(II) intel(0): I2C bus "DVOI2C_B" initialized.
>(II) Loading sub module "tfp410"
>(II) LoadModule: "tfp410"
>(II) Loading /opt/xorg/lib/xorg/modules/drivers/tfp410.so
>(II) Module tfp410: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 5.0
>(II) intel(0): I2C bus "DVOI2C_B" removed.
>(II) intel(0): I2C bus "DVOI2C_E" initialized.
>(II) Loading sub module "ch7017"
>(II) LoadModule: "ch7017"
>(II) Loading /opt/xorg/lib/xorg/modules/drivers/ch7017.so
>(II) Module ch7017: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 5.0
>(II) intel(0): I2C bus "DVOI2C_E" removed.
>(II) intel(0): I2C bus "DVOI2C_E" initialized.
>(II) intel(0): I2C bus "DVOI2C_E" removed.
>(II) intel(0): I2C bus "DVODDC_D" removed.
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 491 520 -hsync -vsync (37.9 kHz)
>(II) intel(0): chosen: dotclock 31500 vco 1008000 ((m 126, m1 20, m2 14), n 4, (p 32, p1 8, p2 4))
>(II) intel(0): I2C bus "CRTDDC_A" initialized.
>(II) intel(0): I2C bus "CRTDDC_A" removed.
>(II) intel(0): I2C bus "CRTDDC_A" initialized.
>(**) intel(0): Option "ddc" "off"
>(II) intel(0): I2C bus "CRTDDC_A" removed.
>(II) intel(0): I2C bus "CRTDDC_D" initialized.
>(**) intel(0): Option "ddc" "off"
>(II) intel(0): I2C bus "CRTDDC_D" removed.
>(II) intel(0): I2C bus "CRTDDC_E" initialized.
>(**) intel(0): Option "ddc" "off"
>(II) intel(0): I2C bus "CRTDDC_E" removed.
>(II) intel(0): EDID for output VGA
>(II) intel(0): Not using default mode "320x175" (doublescan mode not supported)
>(II) intel(0): Not using default mode "320x200" (doublescan mode not supported)
>(II) intel(0): Not using default mode "360x200" (doublescan mode not supported)
>(II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
>(II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
>(II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
>(II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1024x768" (interlace mode not supported)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "576x432" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x480" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x480" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x512" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x512" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x512" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1600x1200" (hsync out of range)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "896x672" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1792x1344" (hsync out of range)
>(II) intel(0): Not using default mode "896x672" (doublescan mode not supported)
>(II) intel(0): Not using default mode "928x696" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1856x1392" (hsync out of range)
>(II) intel(0): Not using default mode "928x696" (doublescan mode not supported)
>(II) intel(0): Not using default mode "960x720" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1920x1440" (hsync out of range)
>(II) intel(0): Not using default mode "960x720" (doublescan mode not supported)
>(II) intel(0): Not using default mode "416x312" (doublescan mode not supported)
>(II) intel(0): Not using default mode "700x525" (doublescan mode not supported)
>(II) intel(0): Not using default mode "700x525" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1920x1440" (hsync out of range)
>(II) intel(0): Not using default mode "960x720" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1024x768" (doublescan mode not supported)
>(II) intel(0): Not using default mode "2048x1536" (hsync out of range)
>(II) intel(0): Not using default mode "1024x768" (doublescan mode not supported)
>(II) intel(0): Not using default mode "2048x1536" (hsync out of range)
>(II) intel(0): Not using default mode "1024x768" (doublescan mode not supported)
>(II) intel(0): Printing probed modes for output VGA
>(II) intel(0): Modeline "1280x1024"x94.5  170.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (100.7 kHz)
>(II) intel(0): Modeline "2048x1536"x60.0  266.95  2048 2200 2424 2800  1536 1537 1540 1589 -hsync +vsync (95.3 kHz)
>(II) intel(0): Modeline "1920x1440"x60.0  234.00  1920 2048 2256 2600  1440 1441 1444 1500 -hsync +vsync (90.0 kHz)
>(II) intel(0): Modeline "1856x1392"x60.0  218.30  1856 1952 2176 2528  1392 1393 1396 1439 -hsync +vsync (86.4 kHz)
>(II) intel(0): Modeline "1792x1344"x60.0  204.80  1792 1920 2120 2448  1344 1345 1348 1394 -hsync +vsync (83.7 kHz)
>(II) intel(0): Modeline "1600x1200"x75.0  202.50  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (93.8 kHz)
>(II) intel(0): Modeline "1600x1200"x70.0  189.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (87.5 kHz)
>(II) intel(0): Modeline "1600x1200"x65.0  175.50  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (81.2 kHz)
>(II) intel(0): Modeline "1600x1200"x60.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz)
>(II) intel(0): Modeline "1400x1050"x74.8  155.80  1400 1464 1784 1912  1050 1052 1064 1090 +hsync +vsync (81.5 kHz)
>(II) intel(0): Modeline "1400x1050"x60.0  122.00  1400 1488 1640 1880  1050 1052 1064 1082 +hsync +vsync (64.9 kHz)
>(II) intel(0): Modeline "1280x1024"x85.0  157.50  1280 1344 1504 1728  1024 1025 1028 1072 +hsync +vsync (91.1 kHz)
>(II) intel(0): Modeline "1280x1024"x75.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz)
>(II) intel(0): Modeline "1280x1024"x60.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz)
>(II) intel(0): Modeline "1280x960"x85.0  148.50  1280 1344 1504 1728  960 961 964 1011 +hsync +vsync (85.9 kHz)
>(II) intel(0): Modeline "1280x960"x60.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz)
>(II) intel(0): Modeline "1152x864"x75.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz)
>(II) intel(0): Modeline "1024x768"x85.0   94.50  1024 1072 1168 1376  768 769 772 808 +hsync +vsync (68.7 kHz)
>(II) intel(0): Modeline "1024x768"x75.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz)
>(II) intel(0): Modeline "1024x768"x70.1   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz)
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) intel(0): Modeline "832x624"x74.6   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz)
>(II) intel(0): Modeline "800x600"x85.1   56.30  800 832 896 1048  600 601 604 631 +hsync +vsync (53.7 kHz)
>(II) intel(0): Modeline "800x600"x72.2   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz)
>(II) intel(0): Modeline "800x600"x75.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz)
>(II) intel(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x480"x85.0   36.00  640 696 752 832  480 481 484 509 -hsync -vsync (43.3 kHz)
>(II) intel(0): Modeline "640x480"x72.8   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz)
>(II) intel(0): Modeline "640x480"x75.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz)
>(II) intel(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): Modeline "720x400"x85.0   35.50  720 756 828 936  400 401 404 446 -hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x400"x85.1   31.50  640 672 736 832  400 401 404 445 -hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x350"x85.1   31.50  640 672 736 832  350 382 385 445 +hsync -vsync (37.9 kHz)
>(II) intel(0): Output VGA connected
>(II) intel(0): Using user preference for initial modes
>(II) intel(0): Output VGA using initial mode 1280x1024
>(II) intel(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
>(II) intel(0): detected 128 kB GTT.
>(II) intel(0): detected 8060 kB stolen memory.
>(==) intel(0): video overlay key set to 0x101fe
>(**) intel(0): Display dimensions: (360, 270) mm
>(**) intel(0): DPI set to (90, 96)
>(II) Loading sub module "fb"
>(II) LoadModule: "fb"
>(II) Loading /opt/xorg/lib/xorg/modules/libfb.so
>(II) Module fb: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	ABI class: X.Org ANSI C Emulation, version 0.4
>(II) intel(0): Comparing regs from server start up to After PreInit
>(==) Depth 24 pixmap format is 32 bpp
>(II) do I need RAC?  No, I don't.
>(II) resource ranges after preInit:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B](OprD)
>	[5] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD)
>	[6] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B](OprD)
>	[7] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[8] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>	[9] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B](OprU)
>	[10] 0	0	0x000003c0 - 0x000003df (0x20) IS[B](OprU)
>(II) intel(0): Kernel reported 238848 total, 1 used
>(II) intel(0): I830CheckAvailableMemory: 955388 kB available
>(**) intel(0): Framebuffer compression disabled
>(**) intel(0): Tiling enabled
>(==) intel(0): VideoRam: 131072 KB
>(II) intel(0): Attempting memory allocation with tiled buffers.
>(II) intel(0): Tiled allocation successful.
>(II) intel(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000
>(II) UXA(0): Driver registered support for the following operations:
>(II)         solid
>(II)         copy
>(II)         composite (RENDER acceleration)
>(==) intel(0): Backing store disabled
>(==) intel(0): Silken mouse enabled
>(II) intel(0): Initializing HW Cursor
>(II) intel(0): xf86BindGARTMemory: bind key 0 at 0x007df000 (pgoffset 2015)
>(II) intel(0): xf86BindGARTMemory: bind key 1 at 0x00825000 (pgoffset 2085)
>(II) intel(0): xf86BindGARTMemory: bind key 2 at 0x01000000 (pgoffset 4096)
>(II) intel(0): Fixed memory allocation layout:
>(II) intel(0): 0x00000000-0x0001ffff: ring buffer (128 kB)
>(II) intel(0): 0x00020000-0x00024fff: HW cursors (20 kB)
>(II) intel(0): 0x00025000-0x00824fff: fake bufmgr (8192 kB)
>(II) intel(0): 0x007df000:            end of stolen memory
>(II) intel(0): 0x00825000-0x00825fff: overlay registers (4 kB, 0x0000000038e2f000 physical
>)
>(II) intel(0): 0x01000000-0x017fffff: front buffer (8192 kB) X tiled
>(II) intel(0): 0x08000000:            end of aperture
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "1280x1024"x94.5  170.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (100.7 kHz)
>(II) intel(0): chosen: dotclock 170666 vco 1024000 ((m 128, m1 20, m2 16), n 4, (p 6, p1 3, p2 2))
>(II) intel(0): Hardware state at EnterVT:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x6ff000ef (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep present)
>(II) intel(0):               C0DRB0: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB1: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB0: 0xbb2c511a (0x511a)
>(II) intel(0):               C1DRB1: 0x694cbb2c (0xbb2c)
>(II) intel(0):               C1DRB2: 0x6f4c694c (0x694c)
>(II) intel(0):               C1DRB3: 0x00066f4c (0x6f4c)
>(II) intel(0):              C0DRA01: 0x00000000 (0x0000)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x01560006 (0x0006)
>(II) intel(0):              C1DRA23: 0x03810156 (0x0156)
>(II) intel(0):           PGETBL_CTL: 0x3ffe0001
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4)
>(II) intel(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) intel(0):         CACHE_MODE_0: 0x00000000
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x0000005f
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80000018 (enabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0x0000b011 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00002000 (8192 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x01000000
>(II) intel(0):             DSPASURF: 0x1408c080
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x04ff03ff (1280, 1024)
>(II) intel(0):            PIPEASTAT: 0x80000207 (status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):    PIPEA_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEA_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPA0: 0x00041410 (n = 4, m1 = 20, m2 = 16)
>(II) intel(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):               DPLL_A: 0x90010000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 3, p2 = 2)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x069704ff (1280 active, 1688 total)
>(II) intel(0):             HBLANK_A: 0x069704ff (1280 start, 1688 end)
>(II) intel(0):              HSYNC_A: 0x059f050f (1296 start, 1440 end)
>(II) intel(0):             VTOTAL_A: 0x042903ff (1024 active, 1066 total)
>(II) intel(0):             VBLANK_A: 0x042903ff (1024 start, 1066 end)
>(II) intel(0):              VSYNC_A: 0x04030400 (1025 start, 1028 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x00000000 (1, 1)
>(II) intel(0):            PIPEBSTAT: 0x00000000 (status:)
>(II) intel(0):    PIPEB_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEB_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):                 FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):               DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             HBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              HSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):             VTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             VBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              VSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b
>(II) intel(0):             VGACNTRL: 0x8020008e (disabled)
>(II) intel(0):               TV_CTL: 0x069704ff
>(II) intel(0):               TV_DAC: 0x069704ff
>(II) intel(0):             TV_CSC_Y: 0x042903ff
>(II) intel(0):            TV_CSC_Y2: 0x04030400
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x04ff03ff
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00130000
>(II) intel(0):          TV_SC_CTL_2: 0x00380400
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x069704ff
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x00000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000000
>(II) intel(0):         MI_ARB_STATE: 0x00000000
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x069704ff
>(II) intel(0):       DPC_AUX_CH_CTL: 0x042903ff
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x04030400
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x04ff03ff
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):             FENCE  0: 0x01000461 ( enabled, X tiled,  128 pitch, 0x01000000 - 0x01800000 (8192kb))
>(II) intel(0):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  3: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  4: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0): pipe A dot 170666 n 4 m1 20 m2 16 p1 3 p2 2
>(II) intel(0): pipe B dot 72000 n 0 m1 0 m2 0 p1 2 p2 2
>(II) intel(0): DumpRegsEnd
>(II) intel(0): Output configuration:
>(II) intel(0):   Pipe A is on
>(II) intel(0):   Display plane A is now enabled and connected to pipe A.
>(II) intel(0):   Output VGA is connected to pipe A
>(II) intel(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>(II) intel(0): Set up overlay video
>(II) intel(0): direct rendering: Disabled
>(WW) intel(0): Option "AccelMethod" is not used
>(WW) intel(0): Option "UseDDCModes" is not used
>(WW) intel(0): Option "UseDefaultModes" is not used
>(--) RandR disabled
>(II) Initializing built-in extension Generic Event Extension
>(II) Initializing built-in extension SHAPE
>(II) Initializing built-in extension MIT-SHM
>(II) Initializing built-in extension XInputExtension
>(II) Initializing built-in extension XTEST
>(II) Initializing built-in extension BIG-REQUESTS
>(II) Initializing built-in extension SYNC
>(II) Initializing built-in extension XKEYBOARD
>(II) Initializing built-in extension XC-MISC
>(II) Initializing built-in extension XINERAMA
>(II) Initializing built-in extension XFIXES
>(II) Initializing built-in extension RENDER
>(II) Initializing built-in extension RANDR
>(II) Initializing built-in extension COMPOSITE
>(II) Initializing built-in extension DAMAGE
>(II) AIGLX: Screen 0 is not DRI2 capable
>(II) AIGLX: Screen 0 is not DRI capable
>(II) AIGLX: Loaded and initialized /opt/xorg/lib/dri/swrast_dri.so
>(II) GLX: Initialized DRISWRAST GL provider for screen 0
>(II) intel(0): Setting screen physical size to 360 x 270
>(**) Option "Protocol" "IntelliMouse"
>(**) MS3: Device: "/dev/gpmdata"
>(**) MS3: Protocol: "IntelliMouse"
>(**) Option "CorePointer"
>(**) MS3: always reports core events
>(**) Option "Device" "/dev/gpmdata"
>(**) Option "Buttons" "5"
>(==) MS3: Emulate3Buttons, Emulate3Timeout: 50
>(**) Option "ZAxisMapping" "4 5"
>(**) MS3: ZAxisMapping: buttons 4 and 5
>(**) MS3: Buttons: 9
>(**) MS3: Sensitivity: 1
>(**) Option "BaudRate" "1200"
>(**) MS3: BaudRate: 1200
>(II) XINPUT: Adding extended input device "MS3" (type: MOUSE)
>(**) MS3: (accel) keeping acceleration scheme 1
>(**) MS3: (accel) acceleration profile 0
>(**) Option "CoreKeyboard"
>(**) Keyboard1: always reports core events
>(**) Option "Protocol" "standard"
>(**) Keyboard1: Protocol: standard
>(**) Option "XkbRules" "base"
>(**) Keyboard1: XkbRules: "base"
>(**) Option "XkbModel" "pc102"
>(**) Keyboard1: XkbModel: "pc102"
>(**) Option "XkbLayout" "de"
>(**) Keyboard1: XkbLayout: "de"
>(**) Option "XkbVariant" "nodeadkeys"
>(**) Keyboard1: XkbVariant: "nodeadkeys"
>(**) Option "XkbOptions" "eurosign:e compose:caps"
>(**) Keyboard1: XkbOptions: "eurosign:e compose:caps"
>(**) Option "CustomKeycodes" "off"
>(**) Keyboard1: CustomKeycodes disabled
>(II) XINPUT: Adding extended input device "Keyboard1" (type: KEYBOARD)
>(II) intel(0): Comparing regs from server start up to After LeaveVT
>(WW) intel(0): Register 0x2000 (FENCE  0) changed from 0x00000000 to 0x01000461
>(WW) intel(0): FENCE  0 before: disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb)
>(WW) intel(0): FENCE  0 after:  enabled, X tiled,  128 pitch, 0x01000000 - 0x01800000 (8192kb)
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x6ff000ef (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep present)
>(II) intel(0):               C0DRB0: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB1: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB0: 0xbb2c511a (0x511a)
>(II) intel(0):               C1DRB1: 0x694cbb2c (0xbb2c)
>(II) intel(0):               C1DRB2: 0x6f4c694c (0x694c)
>(II) intel(0):               C1DRB3: 0x00066f4c (0x6f4c)
>(II) intel(0):              C0DRA01: 0x00000000 (0x0000)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x01560006 (0x0006)
>(II) intel(0):              C1DRA23: 0x03810156 (0x0156)
>(II) intel(0):           PGETBL_CTL: 0x3ffe0001
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4)
>(II) intel(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) intel(0):         CACHE_MODE_0: 0x00000000
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x0000005f
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80008000 (enabled, pipe A, -hsync, -vsync)
>(II) intel(0):                 LVDS: 0x0000b001 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x1408c080
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x00000000 (1, 1)
>(II) intel(0):            PIPEASTAT: 0x80000207 (status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):    PIPEA_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEA_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):               DPLL_A: 0x808b0000 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 13, p2 = 4)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x00000000 (1, 1)
>(II) intel(0):            PIPEBSTAT: 0x00000000 (status:)
>(II) intel(0):    PIPEB_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEB_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):                 FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):               DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             HBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              HSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):             VTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             VBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              VSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b
>(II) intel(0):             VGACNTRL: 0x0020008e (enabled)
>(II) intel(0):               TV_CTL: 0x031f027f
>(II) intel(0):               TV_DAC: 0x03170287
>(II) intel(0):             TV_CSC_Y: 0x020401e7
>(II) intel(0):            TV_CSC_Y2: 0x01eb01e9
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00130000
>(II) intel(0):          TV_SC_CTL_2: 0x00380400
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x031f027f
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x00000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000000
>(II) intel(0):         MI_ARB_STATE: 0x00000000
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x031f027f
>(II) intel(0):       DPC_AUX_CH_CTL: 0x020401e7
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x01eb01e9
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):             FENCE  0: 0x01000461 ( enabled, X tiled,  128 pitch, 0x01000000 - 0x01800000 (8192kb))
>(II) intel(0):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  3: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  4: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0): pipe A dot 25153 n 2 m1 18 m2 7 p1 13 p2 4
>(II) intel(0): pipe B dot 72000 n 0 m1 0 m2 0 p1 2 p2 2
>(II) intel(0): DumpRegsEnd
>(II) intel(0): xf86UnbindGARTMemory: unbind key 0
>(II) intel(0): xf86UnbindGARTMemory: unbind key 1
>(II) intel(0): xf86UnbindGARTMemory: unbind key 2
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) intel(0): xf86BindGARTMemory: bind key 0 at 0x007df000 (pgoffset 2015)
>(II) intel(0): xf86BindGARTMemory: bind key 1 at 0x00825000 (pgoffset 2085)
>(II) intel(0): xf86BindGARTMemory: bind key 2 at 0x01000000 (pgoffset 4096)
>(II) intel(0): Fixed memory allocation layout:
>(II) intel(0): 0x00000000-0x0001ffff: ring buffer (128 kB)
>(II) intel(0): 0x00020000-0x00024fff: HW cursors (20 kB)
>(II) intel(0): 0x00025000-0x00824fff: fake bufmgr (8192 kB)
>(II) intel(0): 0x007df000:            end of stolen memory
>(II) intel(0): 0x00825000-0x00825fff: overlay registers (4 kB, 0x0000000038e2f000 physical
>)
>(II) intel(0): 0x01000000-0x017fffff: front buffer (8192 kB) X tiled
>(II) intel(0): 0x08000000:            end of aperture
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "1280x1024"x94.5  170.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (100.7 kHz)
>(II) intel(0): chosen: dotclock 170666 vco 1024000 ((m 128, m1 20, m2 16), n 4, (p 6, p1 3, p2 2))
>(II) intel(0): Hardware state at EnterVT:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x6ff000ef (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep present)
>(II) intel(0):               C0DRB0: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB1: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB0: 0xbb2c511a (0x511a)
>(II) intel(0):               C1DRB1: 0x694cbb2c (0xbb2c)
>(II) intel(0):               C1DRB2: 0x6f4c694c (0x694c)
>(II) intel(0):               C1DRB3: 0x00066f4c (0x6f4c)
>(II) intel(0):              C0DRA01: 0x00000000 (0x0000)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x01560006 (0x0006)
>(II) intel(0):              C1DRA23: 0x03810156 (0x0156)
>(II) intel(0):           PGETBL_CTL: 0x3ffe0001
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4)
>(II) intel(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) intel(0):         CACHE_MODE_0: 0x00000000
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x0000005f
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80000018 (enabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0x0000b011 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00002000 (8192 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x01000000
>(II) intel(0):             DSPASURF: 0x1408c080
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x04ff03ff (1280, 1024)
>(II) intel(0):            PIPEASTAT: 0x80000207 (status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):    PIPEA_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEA_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPA0: 0x00041410 (n = 4, m1 = 20, m2 = 16)
>(II) intel(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):               DPLL_A: 0x90010000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 3, p2 = 2)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x069704ff (1280 active, 1688 total)
>(II) intel(0):             HBLANK_A: 0x069704ff (1280 start, 1688 end)
>(II) intel(0):              HSYNC_A: 0x059f050f (1296 start, 1440 end)
>(II) intel(0):             VTOTAL_A: 0x042903ff (1024 active, 1066 total)
>(II) intel(0):             VBLANK_A: 0x042903ff (1024 start, 1066 end)
>(II) intel(0):              VSYNC_A: 0x04030400 (1025 start, 1028 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x00000000 (1, 1)
>(II) intel(0):            PIPEBSTAT: 0x00000000 (status:)
>(II) intel(0):    PIPEB_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEB_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):                 FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):               DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             HBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              HSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):             VTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             VBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              VSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b
>(II) intel(0):             VGACNTRL: 0x8020008e (disabled)
>(II) intel(0):               TV_CTL: 0x069704ff
>(II) intel(0):               TV_DAC: 0x069704ff
>(II) intel(0):             TV_CSC_Y: 0x042903ff
>(II) intel(0):            TV_CSC_Y2: 0x04030400
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x04ff03ff
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00130000
>(II) intel(0):          TV_SC_CTL_2: 0x00380400
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x069704ff
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x00000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000000
>(II) intel(0):         MI_ARB_STATE: 0x00000000
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x069704ff
>(II) intel(0):       DPC_AUX_CH_CTL: 0x042903ff
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x04030400
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x04ff03ff
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):             FENCE  0: 0x01000461 ( enabled, X tiled,  128 pitch, 0x01000000 - 0x01800000 (8192kb))
>(II) intel(0):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  3: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  4: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0): pipe A dot 170666 n 4 m1 20 m2 16 p1 3 p2 2
>(II) intel(0): pipe B dot 72000 n 0 m1 0 m2 0 p1 2 p2 2
>(II) intel(0): DumpRegsEnd
>(II) intel(0): Output configuration:
>(II) intel(0):   Pipe A is on
>(II) intel(0):   Display plane A is now enabled and connected to pipe A.
>(II) intel(0):   Output VGA is connected to pipe A
>(II) intel(0): Comparing regs from server start up to After LeaveVT
>(WW) intel(0): Register 0x2000 (FENCE  0) changed from 0x00000000 to 0x01000461
>(WW) intel(0): FENCE  0 before: disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb)
>(WW) intel(0): FENCE  0 after:  enabled, X tiled,  128 pitch, 0x01000000 - 0x01800000 (8192kb)
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x6ff000ef (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep present)
>(II) intel(0):               C0DRB0: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB1: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB0: 0xbb2c511a (0x511a)
>(II) intel(0):               C1DRB1: 0x694cbb2c (0xbb2c)
>(II) intel(0):               C1DRB2: 0x6f4c694c (0x694c)
>(II) intel(0):               C1DRB3: 0x00066f4c (0x6f4c)
>(II) intel(0):              C0DRA01: 0x00000000 (0x0000)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x01560006 (0x0006)
>(II) intel(0):              C1DRA23: 0x03810156 (0x0156)
>(II) intel(0):           PGETBL_CTL: 0x3ffe0001
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4)
>(II) intel(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) intel(0):         CACHE_MODE_0: 0x00000000
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x0000005f
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80008000 (enabled, pipe A, -hsync, -vsync)
>(II) intel(0):                 LVDS: 0x0000b001 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x1408c080
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x00000000 (1, 1)
>(II) intel(0):            PIPEASTAT: 0x80000207 (status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):    PIPEA_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEA_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):               DPLL_A: 0x808b0000 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 13, p2 = 4)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x00000000 (1, 1)
>(II) intel(0):            PIPEBSTAT: 0x00000000 (status:)
>(II) intel(0):    PIPEB_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEB_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):                 FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):               DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             HBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              HSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):             VTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             VBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              VSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b
>(II) intel(0):             VGACNTRL: 0x0020008e (enabled)
>(II) intel(0):               TV_CTL: 0x031f027f
>(II) intel(0):               TV_DAC: 0x03170287
>(II) intel(0):             TV_CSC_Y: 0x020401e7
>(II) intel(0):            TV_CSC_Y2: 0x01eb01e9
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00130000
>(II) intel(0):          TV_SC_CTL_2: 0x00380400
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x031f027f
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x00000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000000
>(II) intel(0):         MI_ARB_STATE: 0x00000000
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x031f027f
>(II) intel(0):       DPC_AUX_CH_CTL: 0x020401e7
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x01eb01e9
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):             FENCE  0: 0x01000461 ( enabled, X tiled,  128 pitch, 0x01000000 - 0x01800000 (8192kb))
>(II) intel(0):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  3: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  4: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0): pipe A dot 25153 n 2 m1 18 m2 7 p1 13 p2 4
>(II) intel(0): pipe B dot 72000 n 0 m1 0 m2 0 p1 2 p2 2
>(II) intel(0): DumpRegsEnd
>(II) intel(0): xf86UnbindGARTMemory: unbind key 0
>(II) intel(0): xf86UnbindGARTMemory: unbind key 1
>(II) intel(0): xf86UnbindGARTMemory: unbind key 2
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) intel(0): xf86BindGARTMemory: bind key 0 at 0x007df000 (pgoffset 2015)
>(II) intel(0): xf86BindGARTMemory: bind key 1 at 0x00825000 (pgoffset 2085)
>(II) intel(0): xf86BindGARTMemory: bind key 2 at 0x01000000 (pgoffset 4096)
>(II) intel(0): Fixed memory allocation layout:
>(II) intel(0): 0x00000000-0x0001ffff: ring buffer (128 kB)
>(II) intel(0): 0x00020000-0x00024fff: HW cursors (20 kB)
>(II) intel(0): 0x00025000-0x00824fff: fake bufmgr (8192 kB)
>(II) intel(0): 0x007df000:            end of stolen memory
>(II) intel(0): 0x00825000-0x00825fff: overlay registers (4 kB, 0x0000000038e2f000 physical
>)
>(II) intel(0): 0x01000000-0x017fffff: front buffer (8192 kB) X tiled
>(II) intel(0): 0x08000000:            end of aperture
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "1280x1024"x94.5  170.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (100.7 kHz)
>(II) intel(0): chosen: dotclock 170666 vco 1024000 ((m 128, m1 20, m2 16), n 4, (p 6, p1 3, p2 2))
>(II) intel(0): Hardware state at EnterVT:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x6ff000ef (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep present)
>(II) intel(0):               C0DRB0: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB1: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB0: 0xbb2c511a (0x511a)
>(II) intel(0):               C1DRB1: 0x694cbb2c (0xbb2c)
>(II) intel(0):               C1DRB2: 0x6f4c694c (0x694c)
>(II) intel(0):               C1DRB3: 0x00066f4c (0x6f4c)
>(II) intel(0):              C0DRA01: 0x00000000 (0x0000)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x01560006 (0x0006)
>(II) intel(0):              C1DRA23: 0x03810156 (0x0156)
>(II) intel(0):           PGETBL_CTL: 0x3ffe0001
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4)
>(II) intel(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) intel(0):         CACHE_MODE_0: 0x00000000
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x0000005f
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80000018 (enabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0x0000b011 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00002000 (8192 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x01000000
>(II) intel(0):             DSPASURF: 0x1408c080
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x04ff03ff (1280, 1024)
>(II) intel(0):            PIPEASTAT: 0x80000207 (status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):    PIPEA_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEA_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPA0: 0x00041410 (n = 4, m1 = 20, m2 = 16)
>(II) intel(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):               DPLL_A: 0x90010000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 3, p2 = 2)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x069704ff (1280 active, 1688 total)
>(II) intel(0):             HBLANK_A: 0x069704ff (1280 start, 1688 end)
>(II) intel(0):              HSYNC_A: 0x059f050f (1296 start, 1440 end)
>(II) intel(0):             VTOTAL_A: 0x042903ff (1024 active, 1066 total)
>(II) intel(0):             VBLANK_A: 0x042903ff (1024 start, 1066 end)
>(II) intel(0):              VSYNC_A: 0x04030400 (1025 start, 1028 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x00000000 (1, 1)
>(II) intel(0):            PIPEBSTAT: 0x00000000 (status:)
>(II) intel(0):    PIPEB_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEB_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):                 FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):               DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             HBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              HSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):             VTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             VBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              VSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b
>(II) intel(0):             VGACNTRL: 0x8020008e (disabled)
>(II) intel(0):               TV_CTL: 0x069704ff
>(II) intel(0):               TV_DAC: 0x069704ff
>(II) intel(0):             TV_CSC_Y: 0x042903ff
>(II) intel(0):            TV_CSC_Y2: 0x04030400
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x04ff03ff
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00130000
>(II) intel(0):          TV_SC_CTL_2: 0x00380400
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x069704ff
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x00000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000000
>(II) intel(0):         MI_ARB_STATE: 0x00000000
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x069704ff
>(II) intel(0):       DPC_AUX_CH_CTL: 0x042903ff
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x04030400
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x04ff03ff
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):             FENCE  0: 0x01000461 ( enabled, X tiled,  128 pitch, 0x01000000 - 0x01800000 (8192kb))
>(II) intel(0):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  3: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  4: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0): pipe A dot 170666 n 4 m1 20 m2 16 p1 3 p2 2
>(II) intel(0): pipe B dot 72000 n 0 m1 0 m2 0 p1 2 p2 2
>(II) intel(0): DumpRegsEnd
>(II) intel(0): Output configuration:
>(II) intel(0):   Pipe A is on
>(II) intel(0):   Display plane A is now enabled and connected to pipe A.
>(II) intel(0):   Output VGA is connected to pipe A
>(II) UnloadModule: "mouse"
>(II) UnloadModule: "kbd"
>(II) intel(0): Comparing regs from server start up to After LeaveVT
>(WW) intel(0): Register 0x2000 (FENCE  0) changed from 0x00000000 to 0x01000461
>(WW) intel(0): FENCE  0 before: disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb)
>(WW) intel(0): FENCE  0 after:  enabled, X tiled,  128 pitch, 0x01000000 - 0x01800000 (8192kb)
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x6ff000ef (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep present)
>(II) intel(0):               C0DRB0: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB1: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB0: 0xbb2c511a (0x511a)
>(II) intel(0):               C1DRB1: 0x694cbb2c (0xbb2c)
>(II) intel(0):               C1DRB2: 0x6f4c694c (0x694c)
>(II) intel(0):               C1DRB3: 0x00066f4c (0x6f4c)
>(II) intel(0):              C0DRA01: 0x00000000 (0x0000)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x01560006 (0x0006)
>(II) intel(0):              C1DRA23: 0x03810156 (0x0156)
>(II) intel(0):           PGETBL_CTL: 0x3ffe0001
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4)
>(II) intel(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) intel(0):         CACHE_MODE_0: 0x00000000
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x0000005f
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80008000 (enabled, pipe A, -hsync, -vsync)
>(II) intel(0):                 LVDS: 0x0000b001 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x1408c080
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x00000000 (1, 1)
>(II) intel(0):            PIPEASTAT: 0x80000207 (status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):    PIPEA_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEA_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) intel(0):               DPLL_A: 0x808b0000 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 13, p2 = 4)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x00000000 (1, 1)
>(II) intel(0):            PIPEBSTAT: 0x00000000 (status:)
>(II) intel(0):    PIPEB_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEB_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_N: 0x00000000
>(II) intel(0):                 FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):                 FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II) intel(0):               DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             HBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              HSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):             VTOTAL_B: 0x00000000 (1 active, 1 total)
>(II) intel(0):             VBLANK_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):              VSYNC_B: 0x00000000 (1 start, 1 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x0000888b
>(II) intel(0):             VGACNTRL: 0x0020008e (enabled)
>(II) intel(0):               TV_CTL: 0x031f027f
>(II) intel(0):               TV_DAC: 0x03170287
>(II) intel(0):             TV_CSC_Y: 0x020401e7
>(II) intel(0):            TV_CSC_Y2: 0x01eb01e9
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00130000
>(II) intel(0):          TV_SC_CTL_2: 0x00380400
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x031f027f
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x00000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000000
>(II) intel(0):         MI_ARB_STATE: 0x00000000
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x031f027f
>(II) intel(0):       DPC_AUX_CH_CTL: 0x020401e7
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x01eb01e9
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):             FENCE  0: 0x01000461 ( enabled, X tiled,  128 pitch, 0x01000000 - 0x01800000 (8192kb))
>(II) intel(0):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  3: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  4: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0): pipe A dot 25153 n 2 m1 18 m2 7 p1 13 p2 4
>(II) intel(0): pipe B dot 72000 n 0 m1 0 m2 0 p1 2 p2 2
>(II) intel(0): DumpRegsEnd
>(II) intel(0): xf86UnbindGARTMemory: unbind key 0
>(II) intel(0): xf86UnbindGARTMemory: unbind key 1
>(II) intel(0): xf86UnbindGARTMemory: unbind key 2

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Attachments on bug 21986: 26282

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