Attachment 26161 Details for Bug 21905 – Xorg.0.log

Xorg.0.log

Xorg.0.log (text/plain), 67.47 KB, created by fridaychen on 2009-05-24 00:48:27 UTC

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Creator: fridaychen

Created: 2009-05-24 00:48:27 UTC

Size: 67.47 KB

patch

obsolete

>
>This is a pre-release version of the X server from The X.Org Foundation.
>It is not supported in any way.
>Bugs may be filed in the bugzilla at http://bugs.freedesktop.org/.
>Select the "xorg" product for bugs you find in this release.
>Before reporting bugs in pre-release versions please check the
>latest version in the X.Org Foundation git repository.
>See http://wiki.x.org/wiki/GitPage for git access instructions.
>
>X.Org X Server 1.6.1.901 (1.6.2 RC 1)
>Release Date: 2009-5-8
>X Protocol Version 11, Revision 0
>Build Operating System: Linux 2.6.26-2-686 i686 Debian
>Current Operating System: Linux mediacenter 2.6.29-2-686 #1 SMP Tue May 19 07:54:03 UTC 2009 i686
>Build Date: 14 May 2009  05:49:41PM
>xorg-server 2:1.6.1.901-2 (jcristau@debian.org) 
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/var/log/Xorg.0.log", Time: Mon May 25 00:35:05 2009
>(==) Using config file: "/etc/X11/xorg.conf"
>(==) No Layout section.  Using the first Screen section.
>(**) |-->Screen "Default Screen" (0)
>(**) |   |-->Monitor "TV"
>(**) |   |-->Device "Configured Video Device"
>(==) Automatically adding devices
>(==) Automatically enabling devices
>(WW) The directory "/usr/share/fonts/X11/cyrillic" does not exist.
>	Entry deleted from font path.
>(==) FontPath set to:
>	/usr/share/fonts/X11/misc,
>	/usr/share/fonts/X11/100dpi/:unscaled,
>	/usr/share/fonts/X11/75dpi/:unscaled,
>	/usr/share/fonts/X11/Type1,
>	/usr/share/fonts/X11/100dpi,
>	/usr/share/fonts/X11/75dpi,
>	/var/lib/defoma/x-ttcidfont-conf.d/dirs/TrueType,
>	built-ins
>(==) ModulePath set to "/usr/lib/xorg/modules"
>(II) Cannot locate a core pointer device.
>(II) Cannot locate a core keyboard device.
>(II) The server relies on HAL to provide the list of input devices.
>	If no devices become available, reconfigure HAL or disable AllowEmptyInput.
>(II) Loader magic: 0x6c0
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.4
>	X.Org Video Driver: 5.0
>	X.Org XInput driver : 4.0
>	X.Org Server Extension : 2.0
>(II) Loader running on linux
>(--) using VT number 7
>
>(--) PCI:*(0@0:2:0) Intel Corporation 82945G/GZ Integrated Graphics Controller rev 2, Mem @ 0xfdf00000/524288, 0xd0000000/268435456, 0xfdf80000/262144, I/O @ 0x0000ff00/8
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) System resource ranges:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>(II) LoadModule: "extmod"
>(II) Loading /usr/lib/xorg/modules/extensions//libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 1.6.1.901, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension SELinux
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "dbe"
>(II) Loading /usr/lib/xorg/modules/extensions//libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 1.6.1.901, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "glx"
>(II) Loading /usr/lib/xorg/modules/extensions//libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 1.6.1.901, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(==) AIGLX enabled
>(II) Loading extension GLX
>(II) LoadModule: "record"
>(II) Loading /usr/lib/xorg/modules/extensions//librecord.so
>(II) Module record: vendor="X.Org Foundation"
>	compiled for 1.6.1.901, module version = 1.13.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension RECORD
>(II) LoadModule: "dri"
>(II) Loading /usr/lib/xorg/modules/extensions//libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 1.6.1.901, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "dri2"
>(II) Loading /usr/lib/xorg/modules/extensions//libdri2.so
>(II) Module dri2: vendor="X.Org Foundation"
>	compiled for 1.6.1.901, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension DRI2
>(II) LoadModule: "intel"
>(II) Loading /usr/lib/xorg/modules/drivers//intel_drv.so
>(II) Module intel: vendor="X.Org Foundation"
>	compiled for 1.6.1, module version = 2.7.1
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 5.0
>(II) intel: Driver for Intel Integrated Graphics Chipsets: i810,
>	i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G,
>	E7221 (i915), 915GM, 945G, 945GM, 945GME, IGD_GM, IGD_G, 965G, G35,
>	965Q, 946GZ, 965GM, 965GME/GLE, G33, Q35, Q33,
>	Mobile IntelÂ® GM45 Express Chipset,
>	Intel Integrated Graphics Device, G45/G43, Q45/Q43, G41
>(II) Primary Device is: PCI 00@00:02:0
>(II) resource ranges after xf86ClaimFixedResources() call:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>(II) resource ranges after probing:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B]
>	[5] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B]
>	[6] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B]
>	[7] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[8] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>	[9] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B]
>	[10] 0	0	0x000003c0 - 0x000003df (0x20) IS[B]
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>(II) Loading /usr/lib/xorg/modules//libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 1.6.1.901, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 5.0
>(II) Loading sub module "ramdac"
>(II) LoadModule: "ramdac"
>(II) Module "ramdac" already built-in
>(**) intel(0): Depth 24, (--) framebuffer bpp 32
>(==) intel(0): RGB weight 888
>(==) intel(0): Default visual is TrueColor
>(**) intel(0): Option "AccelMethod" "xaa"
>(**) intel(0): Option "DRI" "False"
>(**) intel(0): Option "ModeDebug" "True"
>(**) intel(0): Option "LVDSFixedMode" "False"
>(II) intel(0): Integrated Graphics Chipset: Intel(R) 945G
>(--) intel(0): Chipset: "945G"
>(--) intel(0): Linear framebuffer at 0xD0000000
>(--) intel(0): IO registers at addr 0xFDF00000
>(WW) intel(0): libpciaccess reported 0 rom size, guessing 64kB
>(**) intel(0): Using XAA for acceleration
>(II) intel(0): Hardware state on X startup:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x33db4038 (XOR bank/rank, ch2 enh enabled, ch1 enh enabled, ch0 enh disabled, flex disabled, ep not present)
>(II) intel(0):               C0DRB0: 0x000f0202 (0x0202)
>(II) intel(0):               C0DRB1: 0x0000000f (0x000f)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x01300000 (0x0000)
>(II) intel(0):               C1DRB0: 0x0c0b0b0b (0x0b0b)
>(II) intel(0):               C1DRB1: 0x0c0c0c0b (0x0c0b)
>(II) intel(0):               C1DRB2: 0x0d0d0c0c (0x0c0c)
>(II) intel(0):               C1DRB3: 0x0e0d0d0d (0x0d0d)
>(II) intel(0):              C0DRA01: 0x04020130 (0x0130)
>(II) intel(0):              C0DRA23: 0x00080402 (0x0402)
>(II) intel(0):              C1DRA01: 0x100f0e0d (0x0e0d)
>(II) intel(0):              C1DRA23: 0x1211100f (0x100f)
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x80480004 (enabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000010
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x80480004 (enabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0x48000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000280 (640 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x018f02cf (720, 400)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x02cf01df (720, 480)
>(II) intel(0):            PIPEASTAT: 0x80000203 (status: FIFO_UNDERRUN VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):                 FPA0: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0xd4020033 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 4)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x035902cf (720 active, 858 total)
>(II) intel(0):             HBLANK_A: 0x035902cf (720 start, 858 end)
>(II) intel(0):              HSYNC_A: 0x031d02df (736 start, 798 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020c01df (480 start, 525 end)
>(II) intel(0):              VSYNC_A: 0x01ee01e8 (489 start, 495 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00000202 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x84800003 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x0104008e (enabled)
>(II) intel(0):               TV_CTL: 0x00000000
>(II) intel(0):               TV_DAC: 0x00000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x20000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):        FENCE START 0: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 0: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 1: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 1: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 2: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 2: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 3: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 3: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 4: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 4: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 5: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 5: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 6: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 6: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 7: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 7: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 8: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 8: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 9: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 9: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 10: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 10: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 11: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 11: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 12: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 12: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 13: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 13: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 14: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 14: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 15: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 15: 0x00000000 (                                   0x00000000 end)
>(II) intel(0): pipe A dot 108000 n 2 m1 14 m2 8 p1 2 p2 10
>(II) intel(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): 2 display pipes available.
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"
>(II) Module "ddc" already built-in
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"
>(II) Module "i2c" already built-in
>(II) intel(0): Output VGA using monitor section TV
>(**) intel(0): Option "Enable" "True"
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOB" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOB:SDVO Controller B" registered at address 0x70.
>(II) intel(0): I2C bus "SDVOB DDC Bus" initialized.
>(II) intel(0): SDVOB: W: 02                         (SDVO_CMD_GET_DEVICE_CAPS)
>(II) intel(0): SDVOB: R: 04 AA 03 01 01 01 01 00 (Success)
>(II) intel(0): SDVOB: W: 9D                         (SDVO_CMD_GET_SUPP_ENCODE)
>(II) intel(0): SDVOB: R: 00 00                   (Not supported)
>(II) intel(0): Output TMDS-1 using monitor section TV
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 1D                         (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE)
>(II) intel(0): SDVOB: R: C4 09 74 40             (Success)
>(II) intel(0): SDVOB: device VID/DID: 04:AA.03, clock range 25.0MHz - 165.0MHz
>(II) intel(0): SDVOB: 1 input channel
>(II) intel(0): SDVOB: TMDS0 output reported
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOC" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" registered at address 0x72.
>(II) intel(0): No SDVO device found on SDVOC
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" removed.
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOC" removed.
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 08                      (Success)
>(II) intel(0): Current clock rate multiplier: 8
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 01 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 8C 0A D0 8A 20 E0 2D 10 (Success)
>(II) intel(0): SDVOB: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 10 3E 96 00 18 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 8C 0A D0 8A 20 E0 2D 10 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 10 3E 96 00 18 00 00 00 (Success)
>(II) intel(0): Resizable framebuffer: not available (0 2)
>(II) intel(0): EDID for output VGA
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 01 00                   (Success)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): I2C device "SDVOB DDC Bus:E-EDID segment register" registered at address 0x60.
>(II) intel(0): I2C device "SDVOB DDC Bus:ddc2" registered at address 0xA0.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Manufacturer: JVC  Model: 2162  Serial#: 16843009
>(II) intel(0): Year: 2006  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 69  vert.: 39
>(II) intel(0): Gamma: 2.20
>(II) intel(0): DPMS capabilities: Off
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.618 redY: 0.351   greenX: 0.280 greenY: 0.605
>(II) intel(0): blueX: 0.152 blueY: 0.063   whiteX: 0.312 whiteY: 0.329
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 74.2 MHz   Image Size:  692 x 390 mm
>(II) intel(0): h_active: 1920  h_sync: 2008  h_sync_end 2052 h_blank_end 2200 h_border: 0
>(II) intel(0): v_active: 540  v_sync: 542  v_sync_end 547 v_blanking: 562 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 27.0 MHz   Image Size:  520 x 390 mm
>(II) intel(0): h_active: 720  h_sync: 736  h_sync_end 798 h_blank_end 858 h_border: 0
>(II) intel(0): v_active: 480  v_sync: 489  v_sync_end 495 v_blanking: 525 v_border: 0
>(II) intel(0): Monitor name: LT-32LC85
>(II) intel(0): Ranges: V min: 59 V max: 61 Hz, H min: 15 H max: 46 kHz, PixClock max 80 MHz
>(II) intel(0): Number of EDID sections to follow: 1
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff002ac3622101010101
>(II) intel(0): 	00100103804527782a7c119e59479b27
>(II) intel(0): 	10505400000001010101010101010101
>(II) intel(0): 	010101010101011d8018711c1620582c
>(II) intel(0): 	2500b4862100009e8c0ad08a20e02d10
>(II) intel(0): 	103e9600088621000018000000fc004c
>(II) intel(0): 	542d33324c4338350a202020000000fd
>(II) intel(0): 	003b3d0f2e08000a2020202020200193
>(II) intel(0): 	02031a72478502040103060723090707
>(II) intel(0): 	8301000065030c001000011d007251d0
>(II) intel(0): 	1e206e285500b4862100001ed60980a0
>(II) intel(0): 	20e02d101060a2000886210000188c0a
>(II) intel(0): 	d08a20e02d10103e9600b48621000018
>(II) intel(0): 	8c0aa01451f01600267c430008862100
>(II) intel(0): 	00988c0aa01451f01600267c4300b486
>(II) intel(0): 	21000098000000000000000000000018
>(II) intel(0): EDID vendor "JVC", prod id 8546
>(II) intel(0): SDVOB: W: 9D                         (SDVO_CMD_GET_SUPP_ENCODE)
>(II) intel(0): SDVOB: R: 00 00                   (Not supported)
>(II) intel(0): SDVOB: W: 9F 01                      (SDVO_CMD_SET_ENCODE)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): SDVOB: W: 8E 00                      (SDVO_CMD_SET_COLORIMETRY)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): Printing probed modes for output TMDS-1
>(II) intel(0): Modeline "1920x1080"x60.2   74.40  1920 2008 2052 2200  1080 1084 1094 1124 interlace -hsync -vsync (33.8 kHz)
>(II) intel(0): Modeline "1920x540"x120.1   74.25  1920 2008 2052 2200  540 542 547 562 interlace +hsync +vsync (33.8 kHz)
>(II) intel(0): Modeline "720x480"x59.9   27.00  720 736 798 858  480 489 495 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): Output VGA enabled by config file
>(II) intel(0): Output TMDS-1 enabled by config file
>(II) intel(0): Using user preference for initial modes
>(EE) intel(0): Output VGA enabled but has no modes
>(II) intel(0): Output TMDS-1 using initial mode 1920x1080
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 8C 0A D0 8A 20 E0 2D 10 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 8C 0A D0 8A 20 E0 2D 10 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 15 10 3E 96 00 18 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 21 08                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): detected 256 kB GTT.
>(II) intel(0): detected 7932 kB stolen memory.
>(==) intel(0): video overlay key set to 0x101fe
>(==) intel(0): Using gamma correction (1.0, 1.0, 1.0)
>(==) intel(0): DPI set to (96, 96)
>(II) Loading sub module "fb"
>(II) LoadModule: "fb"
>(II) Loading /usr/lib/xorg/modules//libfb.so
>(II) Module fb: vendor="X.Org Foundation"
>	compiled for 1.6.1.901, module version = 1.0.0
>	ABI class: X.Org ANSI C Emulation, version 0.4
>(II) Loading sub module "xaa"
>(II) LoadModule: "xaa"
>(II) Loading /usr/lib/xorg/modules//libxaa.so
>(II) Module xaa: vendor="X.Org Foundation"
>	compiled for 1.6.1.901, module version = 1.2.1
>	ABI class: X.Org Video Driver, version 5.0
>(II) intel(0): Comparing regs from server start up to After PreInit
>(==) Depth 24 pixmap format is 32 bpp
>(II) do I need RAC?  No, I don't.
>(II) resource ranges after preInit:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B](OprD)
>	[5] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD)
>	[6] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B](OprD)
>	[7] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[8] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>	[9] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B](OprU)
>	[10] 0	0	0x000003c0 - 0x000003df (0x20) IS[B](OprU)
>(II) intel(0): Kernel reported 488960 total, 1 used
>(II) intel(0): I830CheckAvailableMemory: 1955836 kB available
>(**) intel(0): Framebuffer compression disabled
>(**) intel(0): Tiling enabled
>(==) intel(0): VideoRam: 262144 KB
>(II) intel(0): Attempting memory allocation with tiled buffers.
>(II) intel(0): Allocating 5760 scanlines for pixmap cache
>(II) intel(0): Tiled allocation successful.
>(II) intel(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000
>(II) intel(0): Using XFree86 Acceleration Architecture (XAA)
>	Screen to screen bit blits
>	Solid filled rectangles
>	8x8 mono pattern filled rectangles
>	Indirect CPU to Screen color expansion
>	Solid Horizontal and Vertical Lines
>	Setting up tile and stipple cache:
>		32 128x128 slots
>		32 256x256 slots
>		16 512x512 slots
>(==) intel(0): Backing store disabled
>(==) intel(0): Silken mouse enabled
>(II) intel(0): Initializing HW Cursor
>(WW) intel(0): drmDropMaster failed: Unknown error 4294967295
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 08                      (Success)
>(II) intel(0): Current clock rate multiplier: 8
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 01 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 8C 0A D0 8A 20 E0 2D 10 (Success)
>(II) intel(0): SDVOB: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 10 3E 96 00 18 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 8C 0A D0 8A 20 E0 2D 10 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 10 3E 96 00 18 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): xf86BindGARTMemory: bind key 0 at 0x007bf000 (pgoffset 1983)
>(II) intel(0): xf86BindGARTMemory: bind key 1 at 0x0082a000 (pgoffset 2090)
>(II) intel(0): xf86BindGARTMemory: bind key 3 at 0x0082b000 (pgoffset 2091)
>(II) intel(0): xf86BindGARTMemory: bind key 2 at 0x04000000 (pgoffset 16384)
>(II) intel(0): Fixed memory allocation layout:
>(II) intel(0): 0x00000000-0x0001ffff: ring buffer (128 kB)
>(II) intel(0): 0x00020000-0x00029fff: HW cursors (40 kB, 0x000000007f820000 physical
>)
>(II) intel(0): 0x0002a000-0x00829fff: fake bufmgr (8192 kB)
>(II) intel(0): 0x007bf000:            end of stolen memory
>(II) intel(0): 0x0082a000-0x0082afff: overlay registers (4 kB, 0x0000000036a34000 physical
>)
>(II) intel(0): 0x0082b000-0x0083afff: xaa scratch (64 kB)
>(II) intel(0): 0x04000000-0x07ffffff: front buffer (65536 kB) X tiled
>(II) intel(0): 0x10000000:            end of aperture
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "1920x1080"x60.2   74.40  1920 2008 2052 2200  1080 1084 1094 1124 interlace -hsync -vsync (33.8 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "1920x1080"x60.2  148.80  1920 2008 2052 2200  1080 1084 1094 1124 interlace -hsync -vsync (67.6 kHz)
>(II) intel(0): chosen: dotclock 148800 vco 1488000 ((m 93, m1 15, m2 6), n 4, (p 10, p1 1, p2 10))
>(II) intel(0): SDVOB: W: 07 01 00 00 00             (SDVO_CMD_SET_IN_OUT_MAP)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): SDVOB: W: 93 01 00                   (SDVO_CMD_SET_HBUF_INDEX)
>(II) intel(0): SDVOB: W: 98 82 02 0D 6F 00 00 00 00 (SDVO_CMD_SET_HBUF_DATA)
>(II) intel(0): SDVOB: W: 98 00 00 00 00 00 00 00 00 (SDVO_CMD_SET_HBUF_DATA)
>(II) intel(0): SDVOB: W: 98 00 00 00 00 00 00 00 00 (SDVO_CMD_SET_HBUF_DATA)
>(II) intel(0): SDVOB: W: 9A C0                      (SDVO_CMD_SET_HBUF_TXRATE)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 10 1D 80 18 71 1C 17 20 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): SDVOB: W: 14 10 1D 80 18 71 1C 17 20 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 15 58 2C 25 00 18 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 21 02                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Hardware state at EnterVT:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x33db4038 (XOR bank/rank, ch2 enh enabled, ch1 enh enabled, ch0 enh disabled, flex disabled, ep not present)
>(II) intel(0):               C0DRB0: 0x000f0202 (0x0202)
>(II) intel(0):               C0DRB1: 0x0000000f (0x000f)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x01300000 (0x0000)
>(II) intel(0):               C1DRB0: 0x0c0b0b0b (0x0b0b)
>(II) intel(0):               C1DRB1: 0x0c0c0c0b (0x0c0b)
>(II) intel(0):               C1DRB2: 0x0d0d0c0c (0x0c0c)
>(II) intel(0):               C1DRB3: 0x0e0d0d0d (0x0d0d)
>(II) intel(0):              C0DRA01: 0x04020130 (0x0130)
>(II) intel(0):              C0DRA23: 0x00080402 (0x0402)
>(II) intel(0):              C1DRA01: 0x100f0e0d (0x0e0d)
>(II) intel(0):              C1DRA23: 0x1211100f (0x100f)
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x80480084 (enabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000010
>(II) intel(0):               DSPARB: 0x00002fdf
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x80480084 (enabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00002000 (8192 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x0437077f (1920, 1080)
>(II) intel(0):             DSPABASE: 0x04000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x077f0437 (1920, 1080)
>(II) intel(0):            PIPEASTAT: 0x80000203 (status: FIFO_UNDERRUN VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):                 FPA0: 0x00040f06 (n = 4, m1 = 15, m2 = 6)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0xd4010010 (enabled, dvo, default clock, DAC/serial mode, p1 = 1, p2 = 10, SDVO mult 2)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x0897077f (1920 active, 2200 total)
>(II) intel(0):             HBLANK_A: 0x0897077f (1920 start, 2200 end)
>(II) intel(0):              HSYNC_A: 0x080307d7 (2008 start, 2052 end)
>(II) intel(0):             VTOTAL_A: 0x0232021b (540 active, 563 total)
>(II) intel(0):             VBLANK_A: 0x0232021b (540 start, 563 end)
>(II) intel(0):              VSYNC_A: 0x0222021d (542 start, 547 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00000202 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x8104008e (disabled)
>(II) intel(0):               TV_CTL: 0x00000000
>(II) intel(0):               TV_DAC: 0x00000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x20000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):        FENCE START 0: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 0: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 1: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 1: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 2: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 2: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 3: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 3: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 4: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 4: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 5: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 5: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 6: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 6: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 7: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 7: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 8: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 8: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 9: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 9: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 10: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 10: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 11: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 11: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 12: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 12: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 13: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 13: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 14: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 14: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 15: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 15: 0x00000000 (                                   0x00000000 end)
>(II) intel(0): pipe A dot 148800 n 4 m1 15 m2 6 p1 1 p2 10
>(II) intel(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): Output configuration:
>(II) intel(0):   Pipe A is on
>(II) intel(0):   Display plane A is now enabled and connected to pipe A.
>(II) intel(0):   Pipe B is off
>(II) intel(0):   Display plane B is now disabled and connected to pipe B.
>(II) intel(0):   Output VGA is connected to pipe none
>(II) intel(0):   Output TMDS-1 is connected to pipe A
>(II) intel(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>(**) Option "dpms" "False"
>(==) intel(0): Intel XvMC decoder disabled
>(II) intel(0): Set up textured video
>(II) intel(0): Set up overlay video
>(II) intel(0): direct rendering: Disabled
>(WW) intel(0): Option "Enable" is not used
>(--) RandR disabled
>(II) Initializing built-in extension Generic Event Extension
>(II) Initializing built-in extension SHAPE
>(II) Initializing built-in extension MIT-SHM
>(II) Initializing built-in extension XInputExtension
>(II) Initializing built-in extension XTEST
>(II) Initializing built-in extension BIG-REQUESTS
>(II) Initializing built-in extension SYNC
>(II) Initializing built-in extension XKEYBOARD
>(II) Initializing built-in extension XC-MISC
>(II) Initializing built-in extension XINERAMA
>(II) Initializing built-in extension XFIXES
>(II) Initializing built-in extension RENDER
>(II) Initializing built-in extension RANDR
>(II) Initializing built-in extension COMPOSITE
>(II) Initializing built-in extension DAMAGE
>SELinux: Disabled on system, not enabling in X server
>(II) AIGLX: Screen 0 is not DRI2 capable
>(II) AIGLX: Screen 0 is not DRI capable
>(II) AIGLX: Loaded and initialized /usr/lib/dri/swrast_dri.so
>(II) GLX: Initialized DRISWRAST GL provider for screen 0
>(II) intel(0): Setting screen physical size to 692 x 390
>(II) intel(0): SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) config/hal: Adding input device Lite-On Tech IBM USB Travel Keyboard with UltraNav
>(II) LoadModule: "evdev"
>(II) Loading /usr/lib/xorg/modules/input//evdev_drv.so
>(II) Module evdev: vendor="X.Org Foundation"
>	compiled for 1.6.1, module version = 2.2.2
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 4.0
>(**) Lite-On Tech IBM USB Travel Keyboard with UltraNav: always reports core events
>(**) Lite-On Tech IBM USB Travel Keyboard with UltraNav: Device: "/dev/input/event3"
>(II) Lite-On Tech IBM USB Travel Keyboard with UltraNav: Found keys
>(II) Lite-On Tech IBM USB Travel Keyboard with UltraNav: Configuring as keyboard
>(II) XINPUT: Adding extended input device "Lite-On Tech IBM USB Travel Keyboard with UltraNav" (type: KEYBOARD)
>(**) Option "xkb_rules" "evdev"
>(**) Option "xkb_model" "pc101"
>(**) Option "xkb_layout" "us"
>(**) Option "xkb_options" "us"
>(II) config/hal: Adding input device Lite-On Tech IBM USB Travel Keyboard with UltraNav
>(**) Lite-On Tech IBM USB Travel Keyboard with UltraNav: always reports core events
>(**) Lite-On Tech IBM USB Travel Keyboard with UltraNav: Device: "/dev/input/event4"
>(II) Lite-On Tech IBM USB Travel Keyboard with UltraNav: Found 21 mouse buttons
>(II) Lite-On Tech IBM USB Travel Keyboard with UltraNav: Found keys
>(II) Lite-On Tech IBM USB Travel Keyboard with UltraNav: Configuring as keyboard
>(**) Lite-On Tech IBM USB Travel Keyboard with UltraNav: YAxisMapping: buttons 4 and 5
>(**) Lite-On Tech IBM USB Travel Keyboard with UltraNav: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>(II) XINPUT: Adding extended input device "Lite-On Tech IBM USB Travel Keyboard with UltraNav" (type: KEYBOARD)
>(**) Option "xkb_rules" "evdev"
>(**) Option "xkb_model" "pc101"
>(**) Option "xkb_layout" "us"
>(**) Option "xkb_options" "us"
>(II) config/hal: Adding input device Synaptics Inc. Composite TouchPad / TrackPoint
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: always reports core events
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: Device: "/dev/input/event6"
>(II) Synaptics Inc. Composite TouchPad / TrackPoint: Found 3 mouse buttons
>(II) Synaptics Inc. Composite TouchPad / TrackPoint: Found x and y relative axes
>(II) Synaptics Inc. Composite TouchPad / TrackPoint: Configuring as mouse
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: YAxisMapping: buttons 4 and 5
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>(II) XINPUT: Adding extended input device "Synaptics Inc. Composite TouchPad / TrackPoint" (type: MOUSE)
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: (accel) keeping acceleration scheme 1
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: (accel) filter chain progression: 2.00
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: (accel) filter stage 0: 20.00 ms
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: (accel) set acceleration profile 0
>(II) config/hal: Adding input device Synaptics Inc. Composite TouchPad / TrackPoint
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: always reports core events
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: Device: "/dev/input/event5"
>(II) Synaptics Inc. Composite TouchPad / TrackPoint: Found 3 mouse buttons
>(II) Synaptics Inc. Composite TouchPad / TrackPoint: Found x and y relative axes
>(II) Synaptics Inc. Composite TouchPad / TrackPoint: Configuring as mouse
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: YAxisMapping: buttons 4 and 5
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>(II) XINPUT: Adding extended input device "Synaptics Inc. Composite TouchPad / TrackPoint" (type: MOUSE)
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: (accel) keeping acceleration scheme 1
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: (accel) filter chain progression: 2.00
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: (accel) filter stage 0: 20.00 ms
>(**) Synaptics Inc. Composite TouchPad / TrackPoint: (accel) set acceleration profile 0
>(II) intel(0): EDID for output VGA
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 01 00                   (Success)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Manufacturer: JVC  Model: 2162  Serial#: 16843009
>(II) intel(0): Year: 2006  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 69  vert.: 39
>(II) intel(0): Gamma: 2.20
>(II) intel(0): DPMS capabilities: Off
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.618 redY: 0.351   greenX: 0.280 greenY: 0.605
>(II) intel(0): blueX: 0.152 blueY: 0.063   whiteX: 0.312 whiteY: 0.329
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 74.2 MHz   Image Size:  692 x 390 mm
>(II) intel(0): h_active: 1920  h_sync: 2008  h_sync_end 2052 h_blank_end 2200 h_border: 0
>(II) intel(0): v_active: 540  v_sync: 542  v_sync_end 547 v_blanking: 562 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 27.0 MHz   Image Size:  520 x 390 mm
>(II) intel(0): h_active: 720  h_sync: 736  h_sync_end 798 h_blank_end 858 h_border: 0
>(II) intel(0): v_active: 480  v_sync: 489  v_sync_end 495 v_blanking: 525 v_border: 0
>(II) intel(0): Monitor name: LT-32LC85
>(II) intel(0): Ranges: V min: 59 V max: 61 Hz, H min: 15 H max: 46 kHz, PixClock max 80 MHz
>(II) intel(0): Number of EDID sections to follow: 1
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff002ac3622101010101
>(II) intel(0): 	00100103804527782a7c119e59479b27
>(II) intel(0): 	10505400000001010101010101010101
>(II) intel(0): 	010101010101011d8018711c1620582c
>(II) intel(0): 	2500b4862100009e8c0ad08a20e02d10
>(II) intel(0): 	103e9600088621000018000000fc004c
>(II) intel(0): 	542d33324c4338350a202020000000fd
>(II) intel(0): 	003b3d0f2e08000a2020202020200193
>(II) intel(0): 	02031a72478502040103060723090707
>(II) intel(0): 	8301000065030c001000011d007251d0
>(II) intel(0): 	1e206e285500b4862100001ed60980a0
>(II) intel(0): 	20e02d101060a2000886210000188c0a
>(II) intel(0): 	d08a20e02d10103e9600b48621000018
>(II) intel(0): 	8c0aa01451f01600267c430008862100
>(II) intel(0): 	00988c0aa01451f01600267c4300b486
>(II) intel(0): 	21000098000000000000000000000018
>(II) intel(0): EDID vendor "JVC", prod id 8546
>(II) intel(0): Using hsync ranges from config file
>(II) intel(0): Using vrefresh ranges from config file
>(II) intel(0): Printing DDC gathered Modelines:
>(II) intel(0): Modeline "1920x540"x0.0   74.25  1920 2008 2052 2200  540 542 547 562 interlace +hsync +vsync (33.8 kHz)
>(II) intel(0): Modeline "720x480"x0.0   27.00  720 736 798 858  480 489 495 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): EDID vendor "JVC", prod id 8546
>(II) intel(0): SDVOB: W: 9D                         (SDVO_CMD_GET_SUPP_ENCODE)
>(II) intel(0): SDVOB: R: 00 00                   (Not supported)
>(II) intel(0): SDVOB: W: 9F 01                      (SDVO_CMD_SET_ENCODE)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): SDVOB: W: 8E 00                      (SDVO_CMD_SET_COLORIMETRY)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): Printing probed modes for output TMDS-1
>(II) intel(0): Modeline "1920x1080"x60.2   74.40  1920 2008 2052 2200  1080 1084 1094 1124 interlace -hsync -vsync (33.8 kHz)
>(II) intel(0): Modeline "1920x540"x120.1   74.25  1920 2008 2052 2200  540 542 547 562 interlace +hsync +vsync (33.8 kHz)
>(II) intel(0): Modeline "720x480"x59.9   27.00  720 736 798 858  480 489 495 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): EDID for output VGA
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 01 00                   (Success)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Manufacturer: JVC  Model: 2162  Serial#: 16843009
>(II) intel(0): Year: 2006  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 69  vert.: 39
>(II) intel(0): Gamma: 2.20
>(II) intel(0): DPMS capabilities: Off
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.618 redY: 0.351   greenX: 0.280 greenY: 0.605
>(II) intel(0): blueX: 0.152 blueY: 0.063   whiteX: 0.312 whiteY: 0.329
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 74.2 MHz   Image Size:  692 x 390 mm
>(II) intel(0): h_active: 1920  h_sync: 2008  h_sync_end 2052 h_blank_end 2200 h_border: 0
>(II) intel(0): v_active: 540  v_sync: 542  v_sync_end 547 v_blanking: 562 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 27.0 MHz   Image Size:  520 x 390 mm
>(II) intel(0): h_active: 720  h_sync: 736  h_sync_end 798 h_blank_end 858 h_border: 0
>(II) intel(0): v_active: 480  v_sync: 489  v_sync_end 495 v_blanking: 525 v_border: 0
>(II) intel(0): Monitor name: LT-32LC85
>(II) intel(0): Ranges: V min: 59 V max: 61 Hz, H min: 15 H max: 46 kHz, PixClock max 80 MHz
>(II) intel(0): Number of EDID sections to follow: 1
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff002ac3622101010101
>(II) intel(0): 	00100103804527782a7c119e59479b27
>(II) intel(0): 	10505400000001010101010101010101
>(II) intel(0): 	010101010101011d8018711c1620582c
>(II) intel(0): 	2500b4862100009e8c0ad08a20e02d10
>(II) intel(0): 	103e9600088621000018000000fc004c
>(II) intel(0): 	542d33324c4338350a202020000000fd
>(II) intel(0): 	003b3d0f2e08000a2020202020200193
>(II) intel(0): 	02031a72478502040103060723090707
>(II) intel(0): 	8301000065030c001000011d007251d0
>(II) intel(0): 	1e206e285500b4862100001ed60980a0
>(II) intel(0): 	20e02d101060a2000886210000188c0a
>(II) intel(0): 	d08a20e02d10103e9600b48621000018
>(II) intel(0): 	8c0aa01451f01600267c430008862100
>(II) intel(0): 	00988c0aa01451f01600267c4300b486
>(II) intel(0): 	21000098000000000000000000000018
>(II) intel(0): EDID vendor "JVC", prod id 8546
>(II) intel(0): Using hsync ranges from config file
>(II) intel(0): Using vrefresh ranges from config file
>(II) intel(0): Printing DDC gathered Modelines:
>(II) intel(0): Modeline "1920x540"x0.0   74.25  1920 2008 2052 2200  540 542 547 562 interlace +hsync +vsync (33.8 kHz)
>(II) intel(0): Modeline "720x480"x0.0   27.00  720 736 798 858  480 489 495 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): EDID vendor "JVC", prod id 8546
>(II) intel(0): SDVOB: W: 9D                         (SDVO_CMD_GET_SUPP_ENCODE)
>(II) intel(0): SDVOB: R: 00 00                   (Not supported)
>(II) intel(0): SDVOB: W: 9F 01                      (SDVO_CMD_SET_ENCODE)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): SDVOB: W: 8E 00                      (SDVO_CMD_SET_COLORIMETRY)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): Printing probed modes for output TMDS-1
>(II) intel(0): Modeline "1920x1080"x60.2   74.40  1920 2008 2052 2200  1080 1084 1094 1124 interlace -hsync -vsync (33.8 kHz)
>(II) intel(0): Modeline "1920x540"x120.1   74.25  1920 2008 2052 2200  540 542 547 562 interlace +hsync +vsync (33.8 kHz)
>(II) intel(0): Modeline "720x480"x59.9   27.00  720 736 798 858  480 489 495 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): EDID for output VGA
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 01 00                   (Success)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(EE) intel(0): Unable to write to SDVOCTRL_E for SDVOB Slave 0x70.
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Manufacturer: JVC  Model: 2162  Serial#: 16843009
>(II) intel(0): Year: 2006  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 69  vert.: 39
>(II) intel(0): Gamma: 2.20
>(II) intel(0): DPMS capabilities: Off
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.618 redY: 0.351   greenX: 0.280 greenY: 0.605
>(II) intel(0): blueX: 0.152 blueY: 0.063   whiteX: 0.312 whiteY: 0.329
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 74.2 MHz   Image Size:  692 x 390 mm
>(II) intel(0): h_active: 1920  h_sync: 2008  h_sync_end 2052 h_blank_end 2200 h_border: 0
>(II) intel(0): v_active: 540  v_sync: 542  v_sync_end 547 v_blanking: 562 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 27.0 MHz   Image Size:  520 x 390 mm
>(II) intel(0): h_active: 720  h_sync: 736  h_sync_end 798 h_blank_end 858 h_border: 0
>(II) intel(0): v_active: 480  v_sync: 489  v_sync_end 495 v_blanking: 525 v_border: 0
>(II) intel(0): Monitor name: LT-32LC85
>(II) intel(0): Ranges: V min: 59 V max: 61 Hz, H min: 15 H max: 46 kHz, PixClock max 80 MHz
>(II) intel(0): Number of EDID sections to follow: 1
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff002ac3622101010101
>(II) intel(0): 	00100103804527782a7c119e59479b27
>(II) intel(0): 	10505400000001010101010101010101
>(II) intel(0): 	010101010101011d8018711c1620582c
>(II) intel(0): 	2500b4862100009e8c0ad08a20e02d10
>(II) intel(0): 	103e9600088621000018000000fc004c
>(II) intel(0): 	542d33324c4338350a202020000000fd
>(II) intel(0): 	003b3d0f2e08000a2020202020200193
>(II) intel(0): 	02031a72478502040103060723090707
>(II) intel(0): 	8301000065030c001000011d007251d0
>(II) intel(0): 	1e206e285500b4862100001ed60980a0
>(II) intel(0): 	20e02d101060a2000886210000188c0a
>(II) intel(0): 	d08a20e02d10103e9600b48621000018
>(II) intel(0): 	8c0aa01451f01600267c430008862100
>(II) intel(0): 	00988c0aa01451f01600267c4300b486
>(II) intel(0): 	21000098000000000000000000000018
>(II) intel(0): EDID vendor "JVC", prod id 8546
>(II) intel(0): Using hsync ranges from config file
>(II) intel(0): Using vrefresh ranges from config file
>(II) intel(0): Printing DDC gathered Modelines:
>(II) intel(0): Modeline "1920x540"x0.0   74.25  1920 2008 2052 2200  540 542 547 562 interlace +hsync +vsync (33.8 kHz)
>(II) intel(0): Modeline "720x480"x0.0   27.00  720 736 798 858  480 489 495 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): EDID vendor "JVC", prod id 8546
>(II) intel(0): SDVOB: W: 9D                         (SDVO_CMD_GET_SUPP_ENCODE)
>(II) intel(0): SDVOB: R: 00 00                   (Not supported)
>(II) intel(0): SDVOB: W: 9F 01                      (SDVO_CMD_SET_ENCODE)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): SDVOB: W: 8E 00                      (SDVO_CMD_SET_COLORIMETRY)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): Printing probed modes for output TMDS-1
>(II) intel(0): Modeline "1920x1080"x60.2   74.40  1920 2008 2052 2200  1080 1084 1094 1124 interlace -hsync -vsync (33.8 kHz)
>(II) intel(0): Modeline "1920x540"x120.1   74.25  1920 2008 2052 2200  540 542 547 562 interlace +hsync +vsync (33.8 kHz)
>(II) intel(0): Modeline "720x480"x59.9   27.00  720 736 798 858  480 489 495 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)

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Attachments on bug 21905: 26161 | 26162

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