Attachment 25815 Details for Bug 21539 – intel reg dumper output as requested

intel reg dumper output as requested

reg_dumper_before.txt (text/plain), 7.74 KB, created by Alex Bennee on 2009-05-13 01:07:12 UTC

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Creator: Alex Bennee

Created: 2009-05-13 01:07:12 UTC

Size: 7.74 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):            CHDECMISC: 0x33db4040 (swap bank, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>(II):               C0DRB0: 0x000f0002 (0x0002)
>(II):               C0DRB1: 0x0000000f (0x000f)
>(II):               C0DRB2: 0x00000000 (0x0000)
>(II):               C0DRB3: 0x01c00000 (0x0000)
>(II):               C1DRB0: 0x0c0b0b0b (0x0b0b)
>(II):               C1DRB1: 0x0c0c0c0b (0x0c0b)
>(II):               C1DRB2: 0x0d0d0c0c (0x0c0c)
>(II):               C1DRB3: 0x0e0d0d0d (0x0d0d)
>(II):              C0DRA01: 0x180601c0 (0x01c0)
>(II):              C0DRA23: 0x00201806 (0x1806)
>(II):              C1DRA01: 0x100f0e0d (0x0e0d)
>(II):              C1DRA23: 0x1211100f (0x100f)
>(II):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II):            DPLL_TEST: 0x00010001 ()
>(II):         CACHE_MODE_0: 0x00006820
>(II):              D_STATE: 0x00000000
>(II):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0xc0480084 (enabled, pipe B, stall disabled, detected)
>(II):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
>(II):              SDVOUDI: 0x00000000
>(II):               DSPARB: 0x00001d9c
>(II):               DSPFW1: 0x00000000
>(II):               DSPFW2: 0x00000000
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0x80000010 (enabled, pipe A, -hsync, +vsync)
>(II):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0xc0480084 (enabled, pipe B, no stall, -hsync, -vsync)
>(II):                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000000 (power target: off)
>(II):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x00000000
>(II):        PP_OFF_DELAYS: 0x00000000
>(II):           PP_DIVISOR: 0x00000000
>(II):         PFIT_CONTROL: 0x00000000
>(II):      PFIT_PGM_RATIOS: 0x00000000
>(II):      PORT_HOTPLUG_EN: 0x06040220
>(II):    PORT_HOTPLUG_STAT: 0x00000300
>(II):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II):           DSPASTRIDE: 0x00001a40 (6720 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x0383059f (1440, 900)
>(II):             DSPABASE: 0x007df000
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEASRC: 0x059f0383 (1440, 900)
>(II):            PIPEASTAT: 0x00000203 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II):                 FPA0: 0x00031209 (n = 3, m1 = 18, m2 = 9)
>(II):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_A: 0x94020000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 1)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x076f059f (1440 active, 1904 total)
>(II):             HBLANK_A: 0x076f059f (1440 start, 1904 end)
>(II):              HSYNC_A: 0x068705ef (1520 start, 1672 end)
>(II):             VTOTAL_A: 0x03a50383 (900 active, 934 total)
>(II):             VBLANK_A: 0x03a50383 (900 start, 934 end)
>(II):              VSYNC_A: 0x038c0386 (903 start, 909 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00001a40 (6720 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x0419068f (1680, 1050)
>(II):             DSPBBASE: 0x007df000
>(II):             DSPBSURF: 0x00000000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEBSRC: 0x068f0419 (1680, 1050)
>(II):            PIPEBSTAT: 0x00000202 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS)
>(II):                 FPB0: 0x00021007 (n = 2, m1 = 16, m2 = 7)
>(II):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_B: 0xd4020000 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 1)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x072f068f (1680 active, 1840 total)
>(II):             HBLANK_B: 0x072f068f (1680 start, 1840 end)
>(II):              HSYNC_B: 0x06df06bf (1728 start, 1760 end)
>(II):             VTOTAL_B: 0x04370419 (1050 active, 1080 total)
>(II):             VBLANK_B: 0x04370419 (1050 start, 1080 end)
>(II):              VSYNC_B: 0x0422041c (1053 start, 1059 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00031108
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x00020002
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x00000000
>(II):               TV_DAC: 0x00000000
>(II):             TV_CSC_Y: 0x00000000
>(II):            TV_CSC_Y2: 0x00000000
>(II):             TV_CSC_U: 0x00000000
>(II):            TV_CSC_U2: 0x00000000
>(II):             TV_CSC_V: 0x00000000
>(II):            TV_CSC_V2: 0x00000000
>(II):         TV_CLR_KNOBS: 0x00000000
>(II):         TV_CLR_LEVEL: 0x00000000
>(II):           TV_H_CTL_1: 0x00000000
>(II):           TV_H_CTL_2: 0x00000000
>(II):           TV_H_CTL_3: 0x00000000
>(II):           TV_V_CTL_1: 0x00000000
>(II):           TV_V_CTL_2: 0x00000000
>(II):           TV_V_CTL_3: 0x00000000
>(II):           TV_V_CTL_4: 0x00000000
>(II):           TV_V_CTL_5: 0x00000000
>(II):           TV_V_CTL_6: 0x00000000
>(II):           TV_V_CTL_7: 0x00000000
>(II):          TV_SC_CTL_1: 0x00000000
>(II):          TV_SC_CTL_2: 0x00000000
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00000000
>(II):          TV_WIN_SIZE: 0x00000000
>(II):      TV_FILTER_CTL_1: 0x00000000
>(II):      TV_FILTER_CTL_2: 0x00000000
>(II):      TV_FILTER_CTL_3: 0x00000000
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0x00000000
>(II):         TV_H_LUMA_59: 0x00000000
>(II):        TV_H_CHROMA_0: 0x00000000
>(II):       TV_H_CHROMA_59: 0x00000000
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x00000000
>(II):          FBC_COMMAND: 0x00000000
>(II):           FBC_STATUS: 0x20000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0x00000000
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000200
>(II):         MI_ARB_STATE: 0x00000040
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000000
>(II):       DPB_AUX_CH_CTL: 0x00000000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000000
>(II):       DPC_AUX_CH_CTL: 0x00000000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x00000000
>(II):       DPD_AUX_CH_CTL: 0x00000000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II): pipe A dot 106560 n 3 m1 18 m2 9 p1 2 p2 10
>(II): pipe B dot 118800 n 2 m1 16 m2 7 p1 2 p2 10
>(II): DumpRegsEnd

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Attachments on bug 21539: 25453 | 25454 | 25455 | 25593 | 25594 | 25815

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