Attachment 25518 Details for Bug 20896 – more debug info

[patch] more debug info

i915-kms-init-gating-render-2.patch (text/plain), 11.48 KB, created by Jesse Barnes on 2009-05-05 14:46:50 UTC

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Creator: Jesse Barnes

Created: 2009-05-05 14:46:50 UTC

Size: 11.48 KB

patch

obsolete

>diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
>index 051134c..9fa42dc 100644
>--- a/drivers/gpu/drm/i915/i915_dma.c
>+++ b/drivers/gpu/drm/i915/i915_dma.c
>@@ -986,6 +986,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> 	unsigned long agp_size, prealloc_size;
> 	int fb_bar = IS_I9XX(dev) ? 2 : 0;
> 	int ret = 0;
>+	u16 cmd;
> 
> 	dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL);
> 	if (!dev->devname) {
>@@ -1011,6 +1012,54 @@ static int i915_load_modeset_init(struct drm_device *dev)
> 	/* Basic memrange allocator for stolen space (aka vram) */
> 	drm_mm_init(&dev_priv->vram, 0, prealloc_size);
> 
>+	/* Disable clock gating reported to work incorrectly according to the
>+	 * specs.
>+	 */
>+	if (IS_G4X(dev)) {
>+		u32 dspclk_gate;
>+
>+		I915_WRITE(RENCLK_GATE_D1, 0);
>+		I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
>+		       GS_UNIT_CLOCK_GATE_DISABLE |
>+		       CL_UNIT_CLOCK_GATE_DISABLE);
>+		I915_WRITE(RAMCLK_GATE_D, 0);
>+		dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
>+			OVRUNIT_CLOCK_GATE_DISABLE |
>+			OVCUNIT_CLOCK_GATE_DISABLE;
>+		if (IS_GM45(dev))
>+			dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
>+		I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
>+	} else if (IS_I965GM(dev)) {
>+		I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
>+		I915_WRITE(RENCLK_GATE_D2, 0);
>+		I915_WRITE(DSPCLK_GATE_D, 0);
>+		I915_WRITE(RAMCLK_GATE_D, 0);
>+		I915_WRITE16(DEUC, 0);
>+	} else if (IS_I965G(dev)) {
>+		I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
>+		       I965_RCC_CLOCK_GATE_DISABLE |
>+		       I965_RCPB_CLOCK_GATE_DISABLE |
>+		       I965_ISC_CLOCK_GATE_DISABLE |
>+		       I965_FBC_CLOCK_GATE_DISABLE);
>+		I915_WRITE(RENCLK_GATE_D2, 0);
>+	} else if (IS_I855(dev) || IS_I865G(dev)) {
>+		I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
>+	} else if (IS_I830(dev)) {
>+		I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
>+	}
>+
>+	/* Render Standby might cause hang issue, try always disable it.*/
>+	if (IS_I965GM(dev) || IS_GM45(dev)) {
>+		u32 render_standby;
>+
>+		render_standby = I915_READ(MCHBAR_RENDER_STANDBY);
>+		if (render_standby & RENDER_STANDBY_ENABLE) {
>+			DRM_DEBUG("Disabling render standby.\n");
>+			I915_WRITE(MCHBAR_RENDER_STANDBY,
>+			       (render_standby & (~RENDER_STANDBY_ENABLE)));
>+		}
>+	}
>+
> 	/* Let GEM Manage from end of prealloc space to end of aperture */
> 	i915_gem_do_init(dev, prealloc_size, agp_size);
> 
>@@ -1030,6 +1079,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
> 	if (ret)
> 		goto destroy_ringbuffer;
> 
>+	pci_read_config_word(dev->pdev, PCI_COMMAND, &cmd);
>+	DRM_ERROR("installed IRQ handler, IER (00x%04x): 0x%08x, PCI CMD: 0x%04x\n", IER, I915_READ(IER), cmd);
>+
> 	/* Always safe in the mode setting case. */
> 	/* FIXME: do pre/post-mode set stuff in core KMS code */
> 	dev->vblank_disable_allowed = 1;
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 2506592..7ec1c53 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -199,6 +199,8 @@ typedef struct drm_i915_private {
> 	u32 saveDSPACNTR;
> 	u32 saveDSPBCNTR;
> 	u32 saveDSPARB;
>+	u32 saveFW_BLC;
>+	u32 saveFW_BLC_SELF;
> 	u32 saveRENDERSTANDBY;
> 	u32 saveHWS;
> 	u32 savePIPEACONF;
>@@ -271,7 +273,7 @@ typedef struct drm_i915_private {
> 	u32 saveIMR;
> 	u32 saveCACHE_MODE_0;
> 	u32 saveD_STATE;
>-	u32 saveCG_2D_DIS;
>+	u32 saveDSPCLK_GATE_D;
> 	u32 saveMI_ARB_STATE;
> 	u32 saveSWF0[16];
> 	u32 saveSWF1[16];
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 98bb4c8..02b027b 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -612,6 +612,8 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
> 	I915_WRITE(IMR, dev_priv->irq_mask_reg);
> 	(void) I915_READ(IER);
> 
>+	DRM_ERROR("wrote IER (0x%04x): 0x%08x\n", IER, enable_mask);
>+
> 	opregion_enable_asle(dev);
> 	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
> 
>@@ -638,6 +640,8 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
> 	I915_WRITE(IMR, 0xffffffff);
> 	I915_WRITE(IER, 0x0);
> 
>+	DRM_ERROR("wrote IER (0x%04x): 0x%08x\n", IER, 0);
>+
> 	I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
> 	I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
> 	I915_WRITE(IIR, I915_READ(IIR));
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 5211947..4872e0c 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -525,8 +525,115 @@
> #define   DPLLA_TEST_M_BYPASS		(1 << 2)
> #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
> #define D_STATE		0x6104
>-#define CG_2D_DIS	0x6200
>-#define CG_3D_DIS	0x6204
>+#define DSPCLK_GATE_D		0x6200
>+# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
>+# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
>+# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
>+# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
>+# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
>+# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
>+# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
>+# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
>+# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
>+# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
>+# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
>+# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
>+# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
>+# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
>+# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
>+# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
>+# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
>+# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
>+# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
>+# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
>+# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
>+# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
>+# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
>+# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
>+# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
>+# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
>+# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
>+# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
>+/**
>+ * This bit must be set on the 830 to prevent hangs when turning off the
>+ * overlay scaler.
>+ */
>+# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
>+# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
>+# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
>+# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
>+# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
>+
>+#define RENCLK_GATE_D1		0x6204
>+# define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
>+# define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
>+# define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
>+# define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
>+# define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
>+# define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
>+# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
>+# define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
>+# define MAG_CLOCK_GATE_DISABLE			(1 << 5)
>+/** This bit must be unset on 855,865 */
>+# define MECI_CLOCK_GATE_DISABLE		(1 << 4)
>+# define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
>+# define MEC_CLOCK_GATE_DISABLE			(1 << 2)
>+# define MECO_CLOCK_GATE_DISABLE		(1 << 1)
>+/** This bit must be set on 855,865. */
>+# define SV_CLOCK_GATE_DISABLE			(1 << 0)
>+# define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
>+# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
>+# define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
>+# define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
>+# define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
>+# define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
>+# define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
>+# define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
>+# define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
>+# define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
>+# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
>+# define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
>+# define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
>+# define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
>+# define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
>+# define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
>+# define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
>+
>+# define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
>+/** This bit must always be set on 965G/965GM */
>+# define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
>+# define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
>+# define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
>+# define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
>+# define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
>+# define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
>+/** This bit must always be set on 965G */
>+# define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
>+# define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
>+# define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
>+# define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
>+# define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
>+# define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
>+# define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
>+# define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
>+# define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
>+# define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
>+# define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
>+# define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
>+# define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
>+# define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
>+# define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
>+# define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
>+# define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
>+# define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
>+# define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
>+
>+#define RENCLK_GATE_D2		0x6208
>+#define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
>+#define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
>+#define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
>+#define RAMCLK_GATE_D		0x6210		/* CRL only */
>+#define DEUC			0x6214          /* CRL only */
> 
> /*
>  * Palette regs
>@@ -562,6 +669,7 @@
> 
> /** GM965 GM45 render standby register */
> #define MCHBAR_RENDER_STANDBY	0x111B8
>+#define RENDER_STANDBY_ENABLE	(1 << 30)
> 
> #define PEG_BAND_GAP_DATA	0x14d68
> 
>diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
>index d669cc2..c30d307 100644
>--- a/drivers/gpu/drm/i915/i915_suspend.c
>+++ b/drivers/gpu/drm/i915/i915_suspend.c
>@@ -239,6 +239,10 @@ int i915_save_state(struct drm_device *dev)
> 	/* Display arbitration control */
> 	dev_priv->saveDSPARB = I915_READ(DSPARB);
> 
>+	/* FIFO watermarks */
>+	dev_priv->saveFW_BLC = I915_READ(FW_BLC);
>+	dev_priv->saveFW_BLC_SELF = I915_READ(FW_BLC_SELF);
>+
> 	/* Pipe & plane A info */
> 	dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
> 	dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
>@@ -333,7 +337,7 @@ int i915_save_state(struct drm_device *dev)
> 
> 	/* Clock gating state */
> 	dev_priv->saveD_STATE = I915_READ(D_STATE);
>-	dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
>+	dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
> 
> 	/* Cache mode state */
> 	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
>@@ -371,6 +375,10 @@ int i915_restore_state(struct drm_device *dev)
> 	/* Display arbitration */
> 	I915_WRITE(DSPARB, dev_priv->saveDSPARB);
> 
>+	/* FIFO watermarks */
>+	I915_WRITE(FW_BLC, dev_priv->saveFW_BLC);
>+	I915_WRITE(FW_BLC_SELF, dev_priv->saveFW_BLC_SELF);
>+
> 	/* Pipe & plane A info */
> 	/* Prime the clock */
> 	if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
>@@ -491,7 +499,7 @@ int i915_restore_state(struct drm_device *dev)
> 
> 	/* Clock gating state */
> 	I915_WRITE (D_STATE, dev_priv->saveD_STATE);
>-	I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS);
>+	I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
> 
> 	/* Cache mode state */
> 	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);

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Attachments on bug 20896: 24794 | 25445 | 25490 | 25495 | 25496 | 25499 | 25512 | 25513 | 25518 | 25519 | 25520 | 25525 | 25526 | 25527

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