Attachment 24971 Details for Bug 21217 – register dump before xserver start

reg_before.dump (text/plain), 7.75 KB, created by aszlig on 2009-04-20 09:38:01 UTC

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Creator: aszlig

Created: 2009-04-20 09:38:01 UTC

Size: 7.75 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):            CHDECMISC: 0x33db7431 (XOR bank/rank, ch2 enh enabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep present)
>(II):               C0DRB0: 0x000f0202 (0x0202)
>(II):               C0DRB1: 0x0000000f (0x000f)
>(II):               C0DRB2: 0x00000000 (0x0000)
>(II):               C0DRB3: 0x08040000 (0x0000)
>(II):               C1DRB0: 0x0e0d0d0c (0x0d0c)
>(II):               C1DRB1: 0x0f0e0e0d (0x0e0d)
>(II):               C1DRB2: 0x100f0f0e (0x0f0e)
>(II):               C1DRB3: 0x0e0d100f (0x100f)
>(II):              C0DRA01: 0x02010804 (0x0804)
>(II):              C0DRA23: 0x00000201 (0x0201)
>(II):              C1DRA01: 0x100f0e0d (0x0e0d)
>(II):              C1DRA23: 0x1211100f (0x100f)
>(II):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II):            DPLL_TEST: 0x00010001 ()
>(II):         CACHE_MODE_0: 0x00006820
>(II):              D_STATE: 0x00000000
>(II):        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0x00480004 (disabled, pipe A, stall disabled, detected)
>(II):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
>(II):              SDVOUDI: 0x00000020
>(II):               DSPARB: 0x00001d9c
>(II):               DSPFW1: 0x00000000
>(II):               DSPFW2: 0x00000000
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0xc0008c18 (enabled, pipe B, +hsync, +vsync)
>(II):                 LVDS: 0xc030033c (enabled, pipe B, 18 bit, 2 channels)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x00480004 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000001 (power target: on)
>(II):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x012c07d0
>(II):        PP_OFF_DELAYS: 0x00fa07d0
>(II):           PP_DIVISOR: 0x00270f05
>(II):         PFIT_CONTROL: 0x00000008
>(II):      PFIT_PGM_RATIOS: 0x00000000
>(II):      PORT_HOTPLUG_EN: 0x06040220
>(II):    PORT_HOTPLUG_STAT: 0x00000000
>(II):             DSPACNTR: 0xc0000000 (enabled, pipe A)
>(II):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x03ff04ff (1280, 1024)
>(II):             DSPABASE: 0x00000000
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEASRC: 0x04ff03ff (1280, 1024)
>(II):            PIPEASTAT: 0x00000203 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II):                 FPA0: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
>(II):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_A: 0x94020000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 1)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x06af04ff (1280 active, 1712 total)
>(II):             HBLANK_A: 0x06af04ff (1280 start, 1712 end)
>(II):              HSYNC_A: 0x05d70557 (1368 start, 1496 end)
>(II):             VTOTAL_A: 0x044f03ff (1024 active, 1104 total)
>(II):             VBLANK_A: 0x044f03ff (1024 start, 1104 end)
>(II):              VSYNC_A: 0x04090402 (1027 start, 1034 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00001a40 (6720 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x0419068f (1680, 1050)
>(II):             DSPBBASE: 0x007df000
>(II):             DSPBSURF: 0x00000000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEBSRC: 0x068f0419 (1680, 1050)
>(II):            PIPEBSTAT: 0x00000202 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS)
>(II):                 FPB0: 0x00030e05 (n = 3, m1 = 14, m2 = 5)
>(II):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_B: 0x99026000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 2, p2 = 7, SDVO mult 1)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x072f068f (1680 active, 1840 total)
>(II):             HBLANK_B: 0x072f068f (1680 start, 1840 end)
>(II):              HSYNC_B: 0x06df06bf (1728 start, 1760 end)
>(II):             VTOTAL_B: 0x04370419 (1050 active, 1080 total)
>(II):             VBLANK_B: 0x04370419 (1050 start, 1080 end)
>(II):              VSYNC_B: 0x0431041b (1052 start, 1074 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00031108
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x00020002
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x000c0000
>(II):               TV_DAC: 0x70000000
>(II):             TV_CSC_Y: 0x0332012d
>(II):            TV_CSC_Y2: 0x07d30104
>(II):             TV_CSC_U: 0x0733052d
>(II):            TV_CSC_U2: 0x05c70200
>(II):             TV_CSC_V: 0x0340030c
>(II):            TV_CSC_V2: 0x06d00200
>(II):         TV_CLR_KNOBS: 0x00606000
>(II):         TV_CLR_LEVEL: 0x010b00e1
>(II):           TV_H_CTL_1: 0x00400359
>(II):           TV_H_CTL_2: 0x80480022
>(II):           TV_H_CTL_3: 0x007c0344
>(II):           TV_V_CTL_1: 0x00f01415
>(II):           TV_V_CTL_2: 0x00060607
>(II):           TV_V_CTL_3: 0x80120001
>(II):           TV_V_CTL_4: 0x000900f0
>(II):           TV_V_CTL_5: 0x000a00f0
>(II):           TV_V_CTL_6: 0x000900f0
>(II):           TV_V_CTL_7: 0x000a00f0
>(II):          TV_SC_CTL_1: 0xc1710087
>(II):          TV_SC_CTL_2: 0x6b405140
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00360024
>(II):          TV_WIN_SIZE: 0x02640198
>(II):      TV_FILTER_CTL_1: 0x800010bb
>(II):      TV_FILTER_CTL_2: 0x00028283
>(II):      TV_FILTER_CTL_3: 0x00014141
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0xb1403000
>(II):         TV_H_LUMA_59: 0x0000b060
>(II):        TV_H_CHROMA_0: 0xb1403000
>(II):       TV_H_CHROMA_59: 0x0000b060
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x00000000
>(II):          FBC_COMMAND: 0x00000000
>(II):           FBC_STATUS: 0x20000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0x00000000
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000200
>(II):         MI_ARB_STATE: 0x00000040
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000000
>(II):       DPB_AUX_CH_CTL: 0x00000000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000000
>(II):       DPC_AUX_CH_CTL: 0x00000000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x00000000
>(II):       DPD_AUX_CH_CTL: 0x00000000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II): pipe A dot 108000 n 2 m1 14 m2 8 p1 2 p2 10
>(II): pipe B dot 124285 n 3 m1 14 m2 5 p1 2 p2 7
>(II): DumpRegsEnd

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Attachments on bug 21217: 24847 | 24848 | 24971 | 24972 | 25005

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