Attachment 24064 Details for Bug 18358 – just for completeness, the intel_reg_dumper output with the fix applied

just for completeness, the intel_reg_dumper output with the fix applied

intrepid.fixed.dump (text/plain), 7.21 KB, created by Adam Gundy on 2009-03-19 19:31:54 UTC

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Creator: Adam Gundy

Created: 2009-03-19 19:31:54 UTC

Size: 7.21 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4)
>(II):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II):         CACHE_MODE_0: 0x00000000
>(II):              D_STATE: 0x0000030f
>(II):        DSPCLK_GATE_D: 0x0000ff7f (clock gates disabled: DPFUNIT DPBMUNIT DPLSUNIT DPLUNIT DPOUNIT DPBUNIT DCUNIT DPUNIT OVHUNIT DPIOUNIT OVFUNIT OVBUNIT OVRUNIT OVCUNIT OVUUNIT OVLUNIT)
>(II):       RENCLK_GATE_D1: 0x00003fff
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II):              SDVOUDI: 0x00000000
>(II):               DSPARB: 0x00013e35
>(II):               DSPFW1: 0x00000000
>(II):               DSPFW2: 0x00000000
>(II):               DSPFW3: 0x00000000
>(II):           FWATER_BLC: 0x01080108
>(II):          FWATER_BLC2: 0x00000108
>(II):                 ADPA: 0x00000c00 (disabled, pipe A, -hsync, -vsync)
>(II):                 LVDS: 0xc0300300 (enabled, pipe B, 18 bit, 1 channel)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000001 (power target: on)
>(II):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II):         PFIT_CONTROL: 0x00000008
>(II):      PFIT_PGM_RATIOS: 0x00000000
>(II):      PORT_HOTPLUG_EN: 0x00000000
>(II):    PORT_HOTPLUG_STAT: 0x00000000
>(II):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II):           DSPASTRIDE: 0x00002000 (8192 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x01df027f (640, 480)
>(II):             DSPABASE: 0x01000000
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEASRC: 0x027f01df (640, 480)
>(II):            PIPEASTAT: 0x00020207 (status: VBLANK_INT_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II):                 FPA0: 0x0004140e (n = 4, m1 = 20, m2 = 14)
>(II):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II):               DPLL_A: 0x90860000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 8, p2 = 4)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x033f027f (640 active, 832 total)
>(II):             HBLANK_A: 0x033f027f (640 start, 832 end)
>(II):              HSYNC_A: 0x02bf0297 (664 start, 704 end)
>(II):             VTOTAL_A: 0x020701df (480 active, 520 total)
>(II):             VBLANK_A: 0x020701e8 (489 start, 520 end)
>(II):              VSYNC_A: 0x01ea01e8 (489 start, 491 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00002000 (8192 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x031f04ff (1280, 800)
>(II):             DSPBBASE: 0x01000000
>(II):             DSPBSURF: 0x00000000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEBSRC: 0x04ff031f (1280, 800)
>(II):            PIPEBSTAT: 0x00020202 (status: VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS)
>(II):                 FPB0: 0x0006120e (n = 6, m1 = 18, m2 = 14)
>(II):                 FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II):               DPLL_B: 0x90016000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 1, p2 = 14)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x057f04ff (1280 active, 1408 total)
>(II):             HBLANK_B: 0x057f04ff (1280 start, 1408 end)
>(II):              HSYNC_B: 0x05340514 (1301 start, 1333 end)
>(II):             VTOTAL_B: 0x032f031f (800 active, 816 total)
>(II):             VBLANK_B: 0x032f031f (800 start, 816 end)
>(II):              VSYNC_B: 0x03270323 (804 start, 808 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00021207
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x0000888b
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x00000000
>(II):               TV_DAC: 0x00000000
>(II):             TV_CSC_Y: 0x00000000
>(II):            TV_CSC_Y2: 0x00000000
>(II):             TV_CSC_U: 0x00000000
>(II):            TV_CSC_U2: 0x00000000
>(II):             TV_CSC_V: 0x00000000
>(II):            TV_CSC_V2: 0x00000000
>(II):         TV_CLR_KNOBS: 0x00000000
>(II):         TV_CLR_LEVEL: 0x00000000
>(II):           TV_H_CTL_1: 0x00000000
>(II):           TV_H_CTL_2: 0x00000000
>(II):           TV_H_CTL_3: 0x00000000
>(II):           TV_V_CTL_1: 0x00000000
>(II):           TV_V_CTL_2: 0x00000000
>(II):           TV_V_CTL_3: 0x00000000
>(II):           TV_V_CTL_4: 0x00000000
>(II):           TV_V_CTL_5: 0x00000000
>(II):           TV_V_CTL_6: 0x00000000
>(II):           TV_V_CTL_7: 0x00000000
>(II):          TV_SC_CTL_1: 0x00000000
>(II):          TV_SC_CTL_2: 0x00000000
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00000000
>(II):          TV_WIN_SIZE: 0x00000000
>(II):      TV_FILTER_CTL_1: 0x00000000
>(II):      TV_FILTER_CTL_2: 0x00000000
>(II):      TV_FILTER_CTL_3: 0x00000000
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0x00000000
>(II):         TV_H_LUMA_59: 0x00000000
>(II):        TV_H_CHROMA_0: 0x00000000
>(II):       TV_H_CHROMA_59: 0x00000000
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x00000000
>(II):          FBC_COMMAND: 0x00000000
>(II):           FBC_STATUS: 0x20000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0x00000000
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000000
>(II):         MI_ARB_STATE: 0x00000000
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000000
>(II):       DPB_AUX_CH_CTL: 0x00000000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000000
>(II):       DPC_AUX_CH_CTL: 0x00000000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x00000000
>(II):       DPD_AUX_CH_CTL: 0x00000000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II): pipe A dot 31500 n 4 m1 20 m2 14 p1 8 p2 4
>(II): pipe B dot 68357 n 6 m1 18 m2 14 p1 1 p2 14
>(II): DumpRegsEnd

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Attachments on bug 18358: 20021 | 20064 | 21283 | 22327 | 22789 | 22790 | 22791 | 23742 | 24064

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