Attachment 23164 Details for Bug 20241 – Xorg.0.log with debug

Xorg.0.log with debug

Xorg.0.log (text/plain), 75.75 KB, created by mft on 2009-02-21 12:58:21 UTC

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Creator: mft

Created: 2009-02-21 12:58:21 UTC

Size: 75.75 KB

patch

obsolete

>
>This is a pre-release version of the X server from The X.Org Foundation.
>It is not supported in any way.
>Bugs may be filed in the bugzilla at http://bugs.freedesktop.org/.
>Select the "xorg" product for bugs you find in this release.
>Before reporting bugs in pre-release versions please check the
>latest version in the X.Org Foundation git repository.
>See http://wiki.x.org/wiki/GitPage for git access instructions.
>
>X.Org X Server 1.6.99.1
>Release Date: (unreleased)
>X Protocol Version 11, Revision 0
>Build Operating System: Linux 2.6.29-desktop-0.rc5.1mnb x86_64 
>Current Operating System: Linux localhost 2.6.29-desktop-0.rc5.1mnb #1 SMP Mon Feb 16 16:21:27 EST 2009 x86_64
>Build Date: 21 February 2009  09:15:52AM
> 
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/home/neil/xorg/build/var/log/Xorg.0.log", Time: Sat Feb 21 20:43:24 2009
>(==) Using config file: "/etc/X11/xorg.conf"
>(==) ServerLayout "X.org Configured"
>(**) |-->Screen "Screen0" (0)
>(**) |   |-->Monitor "Monitor0"
>(**) |   |-->Device "Card0"
>(**) |-->Input Device "Mouse0"
>(**) |-->Input Device "Keyboard0"
>(==) Not automatically adding devices
>(==) Not automatically enabling devices
>(WW) The directory "/home/neil/xorg/build/lib/X11/fonts/misc/" does not exist.
>	Entry deleted from font path.
>(WW) The directory "/home/neil/xorg/build/lib/X11/fonts/TTF/" does not exist.
>	Entry deleted from font path.
>(WW) The directory "/home/neil/xorg/build/lib/X11/fonts/OTF" does not exist.
>	Entry deleted from font path.
>(WW) The directory "/home/neil/xorg/build/lib/X11/fonts/Type1/" does not exist.
>	Entry deleted from font path.
>(WW) The directory "/home/neil/xorg/build/lib/X11/fonts/100dpi/" does not exist.
>	Entry deleted from font path.
>(WW) The directory "/home/neil/xorg/build/lib/X11/fonts/75dpi/" does not exist.
>	Entry deleted from font path.
>(==) FontPath set to:
>	built-ins
>(==) ModulePath set to "/home/neil/xorg/build/lib/xorg/modules"
>(II) Loader magic: 0x7c2060
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.4
>	X.Org Video Driver: 5.0
>	X.Org XInput driver : 5.0
>	X.Org Server Extension : 2.0
>(--) using VT number 7
>
>(--) PCI:*(0@0:2:0) unknown vendor (0x8086) unknown chipset (0x2e22) rev 3, Mem @ 0xfe400000/4194304, 0xd0000000/268435456, I/O @ 0x0000ec00/8
>(--) PCI: (0@0:2:1) unknown vendor (0x8086) unknown chipset (0x2e23) rev 3, Mem @ 0xfe800000/1048576
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) System resource ranges:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>(II) "extmod" will be loaded. This was enabled by default and also specified in the config file.
>(II) "dbe" will be loaded. This was enabled by default and also specified in the config file.
>(II) "glx" will be loaded. This was enabled by default and also specified in the config file.
>(II) "dri" will be loaded. This was enabled by default and also specified in the config file.
>(II) "dri2" will be loaded. This was enabled by default and also specified in the config file.
>(II) LoadModule: "dri2"
>(II) Loading /home/neil/xorg/build/lib/xorg/modules/extensions/libdri2.so
>(II) Module dri2: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension DRI2
>(II) LoadModule: "dbe"
>(II) Loading /home/neil/xorg/build/lib/xorg/modules/extensions/libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "dri"
>(II) Loading /home/neil/xorg/build/lib/xorg/modules/extensions/libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "glx"
>(II) Loading /home/neil/xorg/build/lib/xorg/modules/extensions/libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(==) AIGLX enabled
>(II) Loading extension GLX
>(II) LoadModule: "extmod"
>(II) Loading /home/neil/xorg/build/lib/xorg/modules/extensions/libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "intel"
>(II) Loading /home/neil/xorg/build/lib/xorg/modules/drivers/intel_drv.so
>(II) Module intel: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 2.6.99
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 5.0
>(II) LoadModule: "mouse"
>(II) Loading /home/neil/xorg/build/lib/xorg/modules/input/mouse_drv.so
>(II) Module mouse: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.4.0
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 5.0
>(II) LoadModule: "kbd"
>(II) Loading /home/neil/xorg/build/lib/xorg/modules/input/kbd_drv.so
>(II) Module kbd: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.3.2
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 5.0
>(II) intel: Driver for Intel Integrated Graphics Chipsets: i810,
>	i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G,
>	E7221 (i915), 915GM, 945G, 945GM, 945GME, 965G, G35, 965Q, 946GZ,
>	965GM, 965GME/GLE, G33, Q35, Q33,
>	Mobile IntelÂ® GM45 Express Chipset,
>	Intel Integrated Graphics Device, G45/G43, Q45/Q43, G41
>(II) Primary Device is: PCI 00@00:02:0
>(II) resource ranges after xf86ClaimFixedResources() call:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>(II) resource ranges after probing:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B]
>	[5] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B]
>	[6] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B]
>	[7] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[8] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>	[9] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B]
>	[10] 0	0	0x000003c0 - 0x000003df (0x20) IS[B]
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>(II) Loading /home/neil/xorg/build/lib/xorg/modules/libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 5.0
>(==) intel(0): Depth 24, (--) framebuffer bpp 32
>(==) intel(0): RGB weight 888
>(==) intel(0): Default visual is TrueColor
>(**) intel(0): Option "AccelMethod" "UXA"
>(**) intel(0): Option "ModeDebug" "Yes"
>(II) intel(0): Integrated Graphics Chipset: Intel(R) G45/G43
>(--) intel(0): Chipset: "G45/G43"
>(--) intel(0): Linear framebuffer at 0xD0000000
>(--) intel(0): IO registers at addr 0xFE400000
>(WW) intel(0): libpciaccess reported 0 rom size, guessing 64kB
>(**) intel(0): Using UXA for acceleration
>(II) intel(0): Hardware state on X startup:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x00000011 (none, ch2 enh enabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep present)
>(II) intel(0):               C0DRB0: 0x00200010 (0x0010)
>(II) intel(0):               C0DRB1: 0x00200020 (0x0020)
>(II) intel(0):               C0DRB2: 0x00200020 (0x0020)
>(II) intel(0):               C0DRB3: 0x86860020 (0x0020)
>(II) intel(0):               C1DRB0: 0x00100008 (0x0008)
>(II) intel(0):               C1DRB1: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB2: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB3: 0x87870010 (0x0010)
>(II) intel(0):              C0DRA01: 0x00008686 (0x8686)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x00008787 (0x8787)
>(II) intel(0):              C1DRA23: 0x00000000 (0x0000)
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x8000009c (enabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00000018 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00000000
>(II) intel(0):               DSPFW1: 0x3f8f0f0f
>(II) intel(0):               DSPFW2: 0x150f0f0f
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x8000009c (enabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):                 DVOC: 0x00000018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x80000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x06180618
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000b00
>(II) intel(0):             DSPACNTR: 0x18000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000c80 (3200 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0xc0000000 (enabled, active)
>(II) intel(0):             PIPEASRC: 0x027f018f (640, 400)
>(II) intel(0):            PIPEASTAT: 0x80000206 (status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPA0: 0x00021506 (n = 2, m1 = 21, m2 = 6)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0xd4020c00 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
>(II) intel(0):            DPLL_A_MD: 0x00000003
>(II) intel(0):             HTOTAL_A: 0x0853068f (1680 active, 2132 total)
>(II) intel(0):             HBLANK_A: 0x0853068f (1680 start, 2132 end)
>(II) intel(0):              HSYNC_A: 0x07b506f1 (1778 start, 1974 end)
>(II) intel(0):             VTOTAL_A: 0x04820419 (1050 active, 1155 total)
>(II) intel(0):             VBLANK_A: 0x04820419 (1050 start, 1155 end)
>(II) intel(0):              VSYNC_A: 0x0428041e (1055 start, 1065 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, inactive)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04020c00 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 10)
>(II) intel(0):            DPLL_B_MD: 0x00000003
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x0224008e (enabled)
>(II) intel(0):               TV_CTL: 0x00000010
>(II) intel(0):               TV_DAC: 0x00000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0xffffffff
>(II) intel(0):          FBC_LL_BASE: 0xffffffff
>(II) intel(0):          FBC_CONTROL: 0xffffffff
>(II) intel(0):          FBC_COMMAND: 0xffffffff
>(II) intel(0):           FBC_STATUS: 0xffffffff
>(II) intel(0):         FBC_CONTROL2: 0xffffffff
>(II) intel(0):        FBC_FENCE_OFF: 0xffffffff
>(II) intel(0):          FBC_MOD_NUM: 0xffffffff
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x0000001c
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00050000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000018
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00050000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000018
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00050000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):        FENCE START 0: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 0: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 1: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 1: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 2: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 2: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 3: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 3: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 4: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 4: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 5: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 5: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 6: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 6: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 7: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 7: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 8: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 8: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 9: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 9: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 10: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 10: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 11: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 11: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 12: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 12: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 13: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 13: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 14: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 14: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 15: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 15: 0x00000000 (                                   0x00000000 end)
>(II) intel(0): pipe A dot 147600 n 2 m1 21 m2 6 p1 2 p2 10
>(II) intel(0): pipe B dot 100800 n 3 m1 17 m2 8 p1 2 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): 2 display pipes available.
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"
>(II) Module "ddc" already built-in
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"
>(II) Module "i2c" already built-in
>(II) intel(0): Output VGA using monitor section Monitor0
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOB" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOB:SDVO Controller B" registered at address 0x70.
>(II) intel(0): I2C bus "SDVOB DDC Bus" initialized.
>(II) intel(0): SDVOB: W: 02                         (SDVO_CMD_GET_DEVICE_CAPS)
>(II) intel(0): SDVOB: R: 02 41 01 01 01 5D 40 00 (Success)
>(II) intel(0): Output LVDS-1 has no monitor section
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 1D                         (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE)
>(II) intel(0): SDVOB: R: C4 09 20 4E             (Success)
>(II) intel(0): SDVOB: device VID/DID: 02:41.01, clock range 25.0MHz - 200.0MHz
>(II) intel(0): SDVOB: 1 input channel
>(II) intel(0): SDVOB: LVDS0 output reported
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOC" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" registered at address 0x72.
>(II) intel(0): No SDVO device found on SDVOC
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" removed.
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOC" removed.
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): Current clock rate multiplier: 1
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 40 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: A8 39 90 C4 61 1A 69 40 (Success)
>(II) intel(0): SDVOB: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 62 C4 5A 00 18 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 40 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: A8 39 90 C4 61 1A 69 40 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 62 C4 5A 00 18 00 00 00 (Success)
>(II) intel(0): Resizable framebuffer: available (1 4)
>(II) intel(0): I2C bus "CRTDDC_A" initialized.
>(II) intel(0): I2C device "CRTDDC_A:E-EDID segment register" registered at address 0x60.
>(II) intel(0): I2C device "CRTDDC_A:ddc2" registered at address 0xA0.
>(II) intel(0): I2C device "CRTDDC_A:ddc2" removed.
>(II) intel(0): I2C device "CRTDDC_A:E-EDID segment register" removed.
>(II) intel(0): I2C bus "CRTDDC_A" removed.
>(II) intel(0): I2C bus "CRTDDC_D" initialized.
>(II) intel(0): I2C device "CRTDDC_D:E-EDID segment register" registered at address 0x60.
>(II) intel(0): I2C device "CRTDDC_D:ddc2" registered at address 0xA0.
>(II) intel(0): I2C device "CRTDDC_D:ddc2" removed.
>(II) intel(0): I2C device "CRTDDC_D:E-EDID segment register" removed.
>(II) intel(0): I2C bus "CRTDDC_D" removed.
>(II) intel(0): I2C bus "CRTDDC_E" initialized.
>(II) intel(0): I2C device "CRTDDC_E:E-EDID segment register" registered at address 0x60.
>(II) intel(0): I2C device "CRTDDC_E:ddc2" registered at address 0xA0.
>(II) intel(0): I2C device "CRTDDC_E:ddc2" removed.
>(II) intel(0): I2C device "CRTDDC_E:E-EDID segment register" removed.
>(II) intel(0): I2C bus "CRTDDC_E" removed.
>(II) intel(0): EDID for output VGA
>(II) intel(0): Not using default mode "640x350" (vrefresh out of range)
>(II) intel(0): Not using default mode "320x175" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x400" (vrefresh out of range)
>(II) intel(0): Not using default mode "320x200" (doublescan mode not supported)
>(II) intel(0): Not using default mode "720x400" (vrefresh out of range)
>(II) intel(0): Not using default mode "360x200" (doublescan mode not supported)
>(II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1024x768" (interlace mode not supported)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1152x864" (vrefresh out of range)
>(II) intel(0): Not using default mode "576x432" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1280x960" (hsync out of range)
>(II) intel(0): Not using default mode "640x480" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1280x960" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x480" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1280x1024" (hsync out of range)
>(II) intel(0): Not using default mode "640x512" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x512" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x512" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1600x1200" (hsync out of range)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1792x1344" (hsync out of range)
>(II) intel(0): Not using default mode "896x672" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1792x1344" (vrefresh out of range)
>(II) intel(0): Not using default mode "896x672" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1856x1392" (hsync out of range)
>(II) intel(0): Not using default mode "928x696" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1856x1392" (vrefresh out of range)
>(II) intel(0): Not using default mode "928x696" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1920x1440" (hsync out of range)
>(II) intel(0): Not using default mode "960x720" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1920x1440" (vrefresh out of range)
>(II) intel(0): Not using default mode "960x720" (doublescan mode not supported)
>(II) intel(0): Not using default mode "832x624" (vrefresh out of range)
>(II) intel(0): Not using default mode "416x312" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1400x1050" (hsync out of range)
>(II) intel(0): Not using default mode "700x525" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1400x1050" (vrefresh out of range)
>(II) intel(0): Not using default mode "700x525" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1920x1440" (vrefresh out of range)
>(II) intel(0): Not using default mode "960x720" (doublescan mode not supported)
>(II) intel(0): Not using default mode "2048x1536" (hsync out of range)
>(II) intel(0): Not using default mode "1024x768" (doublescan mode not supported)
>(II) intel(0): Not using default mode "2048x1536" (vrefresh out of range)
>(II) intel(0): Not using default mode "1024x768" (doublescan mode not supported)
>(II) intel(0): Not using default mode "2048x1536" (vrefresh out of range)
>(II) intel(0): Not using default mode "1024x768" (doublescan mode not supported)
>(II) intel(0): Printing probed modes for output VGA
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) intel(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 40 00                   (Success)
>(II) intel(0): SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): I2C device "SDVOB DDC Bus:E-EDID segment register" registered at address 0x60.
>(II) intel(0): I2C device "SDVOB DDC Bus:ddc2" registered at address 0xA0.
>(II) intel(0): EDID for output LVDS-1
>(II) intel(0): Not using default mode "640x350" (vrefresh out of range)
>(II) intel(0): Not using default mode "320x175" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x400" (vrefresh out of range)
>(II) intel(0): Not using default mode "320x200" (doublescan mode not supported)
>(II) intel(0): Not using default mode "720x400" (vrefresh out of range)
>(II) intel(0): Not using default mode "360x200" (doublescan mode not supported)
>(II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1024x768" (interlace mode not supported)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1152x864" (vrefresh out of range)
>(II) intel(0): Not using default mode "576x432" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1280x960" (hsync out of range)
>(II) intel(0): Not using default mode "640x480" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1280x960" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x480" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1280x1024" (hsync out of range)
>(II) intel(0): Not using default mode "640x512" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x512" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x512" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1600x1200" (hsync out of range)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1792x1344" (hsync out of range)
>(II) intel(0): Not using default mode "896x672" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1792x1344" (vrefresh out of range)
>(II) intel(0): Not using default mode "896x672" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1856x1392" (hsync out of range)
>(II) intel(0): Not using default mode "928x696" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1856x1392" (vrefresh out of range)
>(II) intel(0): Not using default mode "928x696" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1920x1440" (hsync out of range)
>(II) intel(0): Not using default mode "960x720" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1920x1440" (vrefresh out of range)
>(II) intel(0): Not using default mode "960x720" (doublescan mode not supported)
>(II) intel(0): Not using default mode "832x624" (vrefresh out of range)
>(II) intel(0): Not using default mode "416x312" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1400x1050" (hsync out of range)
>(II) intel(0): Not using default mode "700x525" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1400x1050" (vrefresh out of range)
>(II) intel(0): Not using default mode "700x525" (doublescan mode not supported)
>(II) intel(0): Not using default mode "1920x1440" (vrefresh out of range)
>(II) intel(0): Not using default mode "960x720" (doublescan mode not supported)
>(II) intel(0): Not using default mode "2048x1536" (hsync out of range)
>(II) intel(0): Not using default mode "1024x768" (doublescan mode not supported)
>(II) intel(0): Not using default mode "2048x1536" (vrefresh out of range)
>(II) intel(0): Not using default mode "1024x768" (doublescan mode not supported)
>(II) intel(0): Not using default mode "2048x1536" (vrefresh out of range)
>(II) intel(0): Not using default mode "1024x768" (doublescan mode not supported)
>(II) intel(0): Printing probed modes for output LVDS-1
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) intel(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): Output VGA connected
>(II) intel(0): Output LVDS-1 connected
>(II) intel(0): Using fuzzy aspect match for initial modes
>(II) intel(0): Output VGA using initial mode 1024x768
>(II) intel(0): Output LVDS-1 using initial mode 1024x768
>(II) intel(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 40 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 A8 39 90 C4 61 1A 69 40 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 62 C4 5A 00 18 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 A8 39 90 C4 61 1A 69 40 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 15 62 C4 5A 00 18 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): SDVOB: W: 05 40 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): detected 512 kB GTT.
>(II) intel(0): detected 131068 kB stolen memory.
>(==) intel(0): video overlay key set to 0x101fe
>(==) intel(0): DPI set to (96, 96)
>(II) Loading sub module "fb"
>(II) LoadModule: "fb"
>(II) Loading /home/neil/xorg/build/lib/xorg/modules/libfb.so
>(II) Module fb: vendor="X.Org Foundation"
>	compiled for 1.6.99.1, module version = 1.0.0
>	ABI class: X.Org ANSI C Emulation, version 0.4
>(II) Loading sub module "ramdac"
>(II) LoadModule: "ramdac"
>(II) Module "ramdac" already built-in
>(II) intel(0): Comparing regs from server start up to After PreInit
>(==) Depth 24 pixmap format is 32 bpp
>(II) do I need RAC?  No, I don't.
>(II) resource ranges after preInit:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B](OprD)
>	[5] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD)
>	[6] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B](OprD)
>	[7] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[8] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>	[9] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B](OprU)
>	[10] 0	0	0x000003c0 - 0x000003df (0x20) IS[B](OprU)
>(II) intel(0): Kernel reported 711936 total, 1 used
>(II) intel(0): I830CheckAvailableMemory: 2847740 kB available
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is -1, (No such device)
>drmOpenDevice: open result is -1, (No such device)
>drmOpenDevice: Open failed
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 13, (OK)
>drmOpenByBusid: drmOpenMinor returns 13
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(II) intel(0): [DRI2] Setup complete
>(**) intel(0): Framebuffer compression disabled
>(**) intel(0): Tiling enabled
>(==) intel(0): VideoRam: 262144 KB
>(II) intel(0): Attempting memory allocation with tiled buffers.
>(II) intel(0): Tiled allocation successful.
>(II) intel(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000
>(II) UXA(0): Driver registered support for the following operations:
>(II)         solid
>(II)         copy
>(II)         composite (RENDER acceleration)
>(==) intel(0): Backing store disabled
>(==) intel(0): Silken mouse enabled
>(II) intel(0): Initializing HW Cursor
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): Current clock rate multiplier: 1
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 40 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: A8 39 90 C4 61 1A 69 40 (Success)
>(II) intel(0): SDVOB: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 62 C4 5A 00 18 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 40 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: A8 39 90 C4 61 1A 69 40 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 62 C4 5A 00 18 00 00 00 (Success)
>(II) intel(0): Fixed memory allocation layout:
>(II) intel(0): 0x07fff000:            end of stolen memory
>(II) intel(0): 0x07fff000-0x0fffffff: DRI memory manager (131076 kB)
>(II) intel(0): 0x10000000:            end of aperture
>(II) intel(0): BO memory allocation layout:
>(II) intel(0): 0x07fff000:            start of memory manager
>(II) intel(0): 0x08020000-0x0831ffff: front buffer (3072 kB) X tiled
>(II) intel(0): 0x08420000-0x08429fff: HW cursors (40 kB)
>(II) intel(0): 0x10000000:            end of memory manager
>(WW) intel(0): ESR is 0x00000011, page table error
>(WW) intel(0): PGTBL_ER is 0x00100000, CS instruction GTT PTE
>(WW) intel(0): Existing errors found in hardware state.
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) intel(0): chosen: dotclock 64800 vco 2592000 ((m 81, m1 12, m2 9), n 1, (p 40, p1 4, p2 10))
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Mode for pipe B:
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) intel(0): Adjusted mode for pipe B:
>(II) intel(0): Modeline "1024x768"x60.0  130.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (96.7 kHz)
>(II) intel(0): chosen: dotclock 129600 vco 2592000 ((m 81, m1 12, m2 9), n 1, (p 20, p1 2, p2 10))
>(II) intel(0): SDVOB: W: 07 40 00 00 00             (SDVO_CMD_SET_IN_OUT_MAP)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): SDVOB: W: 11 40 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 64 19 00 40 41 00 26 30 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 18 88 36 00 18 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 64 19 00 40 41 00 26 30 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 15 18 88 36 00 18 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 21 02                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): SDVOB: W: 05 40 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Hardware state at EnterVT:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x00000011 (none, ch2 enh enabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep present)
>(II) intel(0):               C0DRB0: 0x00200010 (0x0010)
>(II) intel(0):               C0DRB1: 0x00200020 (0x0020)
>(II) intel(0):               C0DRB2: 0x00200020 (0x0020)
>(II) intel(0):               C0DRB3: 0x86860020 (0x0020)
>(II) intel(0):               C1DRB0: 0x00100008 (0x0008)
>(II) intel(0):               C1DRB1: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB2: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB3: 0x87870010 (0x0010)
>(II) intel(0):              C0DRA01: 0x00008686 (0x8686)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x00008787 (0x8787)
>(II) intel(0):              C1DRA23: 0x00000000 (0x0000)
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x1000000c (clock gates disabled: VRHUNIT OVRUNIT OVCUNIT)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x000002c0
>(II) intel(0):                SDVOB: 0xc000009c (enabled, pipe B, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00000018 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00000000
>(II) intel(0):               DSPFW1: 0x3f8f0f0f
>(II) intel(0):               DSPFW2: 0x150f0f0f
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80000000 (enabled, pipe A, -hsync, -vsync)
>(II) intel(0):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0xc000009c (enabled, pipe B, no stall, +hsync, +vsync)
>(II) intel(0):                 DVOC: 0x00000018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x06180618
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000b00
>(II) intel(0):             DSPACNTR: 0xd8000400 (enabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00001000 (4096 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x08020000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0xc0000000 (enabled, active)
>(II) intel(0):             PIPEASRC: 0x03ff02ff (1024, 768)
>(II) intel(0):            PIPEASTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPA0: 0x00010c09 (n = 1, m1 = 12, m2 = 9)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0x94080c00 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 4, p2 = 10)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x053f03ff (1024 active, 1344 total)
>(II) intel(0):             HBLANK_A: 0x053f03ff (1024 start, 1344 end)
>(II) intel(0):              HSYNC_A: 0x049f0417 (1048 start, 1184 end)
>(II) intel(0):             VTOTAL_A: 0x032502ff (768 active, 806 total)
>(II) intel(0):             VBLANK_A: 0x032502ff (768 start, 806 end)
>(II) intel(0):              VSYNC_A: 0x03080302 (771 start, 777 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0xd9000400 (enabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00001000 (4096 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x08020000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0xc0000000 (enabled, active)
>(II) intel(0):             PIPEBSRC: 0x03ff02ff (1024, 768)
>(II) intel(0):            PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPB0: 0x00010c09 (n = 1, m1 = 12, m2 = 9)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0xd4020c00 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
>(II) intel(0):            DPLL_B_MD: 0x00000100
>(II) intel(0):             HTOTAL_B: 0x053f03ff (1024 active, 1344 total)
>(II) intel(0):             HBLANK_B: 0x053f03ff (1024 start, 1344 end)
>(II) intel(0):              HSYNC_B: 0x049f0417 (1048 start, 1184 end)
>(II) intel(0):             VTOTAL_B: 0x032502ff (768 active, 806 total)
>(II) intel(0):             VBLANK_B: 0x032502ff (768 start, 806 end)
>(II) intel(0):              VSYNC_B: 0x03080302 (771 start, 777 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x8224008e (disabled)
>(II) intel(0):               TV_CTL: 0x00000010
>(II) intel(0):               TV_DAC: 0x00000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0xffffffff
>(II) intel(0):          FBC_LL_BASE: 0xffffffff
>(II) intel(0):          FBC_CONTROL: 0xffffffff
>(II) intel(0):          FBC_COMMAND: 0xffffffff
>(II) intel(0):           FBC_STATUS: 0xffffffff
>(II) intel(0):         FBC_CONTROL2: 0xffffffff
>(II) intel(0):        FBC_FENCE_OFF: 0xffffffff
>(II) intel(0):          FBC_MOD_NUM: 0xffffffff
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x0000001c
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00050000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000018
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00050000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000018
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00050000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):        FENCE START 0: 0x0802007d ( enabled, X tile walk, 3968 pitch, 0x08020000 start)
>(II) intel(0):          FENCE END 0: 0x0831f000 (                                   0x0831f000 end)
>(II) intel(0):        FENCE START 1: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 1: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 2: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 2: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 3: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 3: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 4: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 4: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 5: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 5: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 6: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 6: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 7: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 7: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 8: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 8: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 9: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 9: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 10: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 10: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 11: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 11: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 12: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 12: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 13: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 13: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 14: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 14: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 15: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 15: 0x00000000 (                                   0x00000000 end)
>(II) intel(0): pipe A dot 64800 n 1 m1 12 m2 9 p1 4 p2 10
>(II) intel(0): pipe B dot 129600 n 1 m1 12 m2 9 p1 2 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): Output configuration:
>(II) intel(0):   Pipe A is on
>(II) intel(0):   Display plane A is now enabled and connected to pipe A.
>(II) intel(0):   Pipe B is on
>(II) intel(0):   Display plane B is now enabled and connected to pipe B.
>(II) intel(0):   Output VGA is connected to pipe A
>(II) intel(0):   Output LVDS-1 is connected to pipe B
>(II) intel(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>(II) intel(0): DPMS enabled
>(==) intel(0): Intel XvMC decoder disabled
>(II) intel(0): Set up textured video
>(II) intel(0): direct rendering: DRI2 Enabled
>(--) RandR disabled
>(II) Initializing built-in extension Generic Event Extension
>(II) Initializing built-in extension SHAPE
>(II) Initializing built-in extension MIT-SHM
>(II) Initializing built-in extension XInputExtension
>(II) Initializing built-in extension XTEST
>(II) Initializing built-in extension BIG-REQUESTS
>(II) Initializing built-in extension SYNC
>(II) Initializing built-in extension XKEYBOARD
>(II) Initializing built-in extension XC-MISC
>(II) Initializing built-in extension XINERAMA
>(II) Initializing built-in extension XFIXES
>(II) Initializing built-in extension RENDER
>(II) Initializing built-in extension RANDR
>(II) Initializing built-in extension COMPOSITE
>(II) Initializing built-in extension DAMAGE
>(II) AIGLX: enabled GLX_MESA_copy_sub_buffer
>(II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control
>(II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects
>(II) AIGLX: Loaded and initialized /home/neil/xorg/build/lib/dri/i965_dri.so
>(II) GLX: Initialized DRI2 GL provider for screen 0
>(II) intel(0): Setting screen physical size to 270 x 203
>(**) Option "Protocol" "auto"
>(**) Option "Device" "/dev/input/mice"
>(II) Mouse0: Setting mouse protocol to "ExplorerPS/2"
>(**) Mouse0: Device: "/dev/input/mice"
>(**) Mouse0: Protocol: "auto"
>(**) Option "CorePointer"
>(**) Mouse0: always reports core events
>(**) Option "Device" "/dev/input/mice"
>(==) Mouse0: Emulate3Buttons, Emulate3Timeout: 50
>(**) Option "ZAxisMapping" "4 5 6 7"
>(**) Mouse0: ZAxisMapping: buttons 4, 5, 6 and 7
>(**) Mouse0: Buttons: 11
>(**) Mouse0: Sensitivity: 1
>(II) XINPUT: Adding extended input device "Mouse0" (type: MOUSE)
>(**) Mouse0: (accel) keeping acceleration scheme 1
>(**) Mouse0: (accel) acceleration profile 0
>(**) Mouse0: (accel) filter chain progression: 2.00
>(**) Mouse0: (accel) filter stage 0: 20.00 ms
>(**) Mouse0: (accel) set acceleration profile 0
>(II) Mouse0: Setting mouse protocol to "ExplorerPS/2"
>(II) Mouse0: ps2EnableDataReporting: succeeded
>(**) Option "CoreKeyboard"
>(**) Keyboard0: always reports core events
>(**) Option "Protocol" "standard"
>(**) Keyboard0: Protocol: standard
>(**) Option "XkbRules" "base"
>(**) Keyboard0: XkbRules: "base"
>(**) Option "XkbModel" "pc105"
>(**) Keyboard0: XkbModel: "pc105"
>(**) Option "XkbLayout" "us"
>(**) Keyboard0: XkbLayout: "us"
>(**) Option "CustomKeycodes" "off"
>(**) Keyboard0: CustomKeycodes disabled
>(II) XINPUT: Adding extended input device "Keyboard0" (type: KEYBOARD)
>(II) intel(0): SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): SDVOB: W: 05 40 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) AIGLX: Suspending AIGLX clients for VT switch
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 40 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 A8 39 90 C4 61 1A 69 40 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 62 C4 5A 00 18 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 A8 39 90 C4 61 1A 69 40 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 15 62 C4 5A 00 18 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): SDVOB: W: 05 40 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Comparing regs from server start up to After LeaveVT
>(WW) intel(0): Register 0x70024 (PIPEASTAT) changed from 0x80000206 to 0x00040202
>(WW) intel(0): PIPEASTAT before: status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS
>(WW) intel(0): PIPEASTAT after: status: SVBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS
>(WW) intel(0): Register 0x71024 (PIPEBSTAT) changed from 0x00000206 to 0x00040000
>(WW) intel(0): PIPEBSTAT before: status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS
>(WW) intel(0): PIPEBSTAT after: status: SVBLANK_INT_ENABLE
>(WW) intel(0): Register 0x3000 (FENCE START 0) changed from 0x00000000 to 0x0802007d
>(WW) intel(0): FENCE START 0 before: disabled, X tile walk,    0 pitch, 0x00000000 start
>(WW) intel(0): FENCE START 0 after:  enabled, X tile walk, 3968 pitch, 0x08020000 start
>(WW) intel(0): Register 0x3004 (FENCE END 0) changed from 0x00000000 to 0x0831f000
>(WW) intel(0): FENCE END 0 before:                                    0x00000000 end
>(WW) intel(0): FENCE END 0 after:                                    0x0831f000 end
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x00000011 (none, ch2 enh enabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep present)
>(II) intel(0):               C0DRB0: 0x00200010 (0x0010)
>(II) intel(0):               C0DRB1: 0x00200020 (0x0020)
>(II) intel(0):               C0DRB2: 0x00200020 (0x0020)
>(II) intel(0):               C0DRB3: 0x86860020 (0x0020)
>(II) intel(0):               C1DRB0: 0x00100008 (0x0008)
>(II) intel(0):               C1DRB1: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB2: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB3: 0x87870010 (0x0010)
>(II) intel(0):              C0DRA01: 0x00008686 (0x8686)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x00008787 (0x8787)
>(II) intel(0):              C1DRA23: 0x00000000 (0x0000)
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x8000009c (enabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00000018 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00000000
>(II) intel(0):               DSPFW1: 0x3f8f0f0f
>(II) intel(0):               DSPFW2: 0x150f0f0f
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x8000009c (enabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):                 DVOC: 0x00000018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x80000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x06180618
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000b00
>(II) intel(0):             DSPACNTR: 0x18000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000c80 (3200 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0xc0000000 (enabled, active)
>(II) intel(0):             PIPEASRC: 0x027f018f (640, 400)
>(II) intel(0):            PIPEASTAT: 0x00040202 (status: SVBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPA0: 0x00021506 (n = 2, m1 = 21, m2 = 6)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0xd4020c00 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
>(II) intel(0):            DPLL_A_MD: 0x00000003
>(II) intel(0):             HTOTAL_A: 0x0853068f (1680 active, 2132 total)
>(II) intel(0):             HBLANK_A: 0x0853068f (1680 start, 2132 end)
>(II) intel(0):              HSYNC_A: 0x07b506f1 (1778 start, 1974 end)
>(II) intel(0):             VTOTAL_A: 0x04820419 (1050 active, 1155 total)
>(II) intel(0):             VBLANK_A: 0x04820419 (1050 start, 1155 end)
>(II) intel(0):              VSYNC_A: 0x0428041e (1055 start, 1065 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, inactive)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00040000 (status: SVBLANK_INT_ENABLE)
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04020c00 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 10)
>(II) intel(0):            DPLL_B_MD: 0x00000003
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x0224008e (enabled)
>(II) intel(0):               TV_CTL: 0x00000010
>(II) intel(0):               TV_DAC: 0x00000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0xffffffff
>(II) intel(0):          FBC_LL_BASE: 0xffffffff
>(II) intel(0):          FBC_CONTROL: 0xffffffff
>(II) intel(0):          FBC_COMMAND: 0xffffffff
>(II) intel(0):           FBC_STATUS: 0xffffffff
>(II) intel(0):         FBC_CONTROL2: 0xffffffff
>(II) intel(0):        FBC_FENCE_OFF: 0xffffffff
>(II) intel(0):          FBC_MOD_NUM: 0xffffffff
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x0000001c
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00050000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000018
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00050000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000018
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00050000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):        FENCE START 0: 0x0802007d ( enabled, X tile walk, 3968 pitch, 0x08020000 start)
>(II) intel(0):          FENCE END 0: 0x0831f000 (                                   0x0831f000 end)
>(II) intel(0):        FENCE START 1: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 1: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 2: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 2: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 3: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 3: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 4: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 4: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 5: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 5: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 6: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 6: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 7: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 7: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 8: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 8: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 9: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 9: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 10: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 10: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 11: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 11: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 12: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 12: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 13: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 13: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 14: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 14: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 15: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 15: 0x00000000 (                                   0x00000000 end)
>(II) intel(0): pipe A dot 147600 n 2 m1 21 m2 6 p1 2 p2 10
>(II) intel(0): pipe B dot 100800 n 3 m1 17 m2 8 p1 2 p2 10
>(II) intel(0): DumpRegsEnd
>(II) UnloadModule: "kbd"
>(II) UnloadModule: "mouse"

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Attachments on bug 20241: 23153 | 23154 | 23164 | 23165 | 23208 | 23261 | 23266 | 23269 | 23270 | 23635 | 23967 | 23973 | 23982 | 24004 | 24022 | 24048 | 24986 | 24990 | 25025 | 25036 | 25037 | 25051 | 25057 | 25155 | 25173 | 25181 | 25209 | 25227

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