Attachment 22244 Details for Bug 19460 – Here Xorg.log with ModeDebug enabled

Here Xorg.log with ModeDebug enabled

Xorg.0.log (text/plain), 48.32 KB, created by Nuzhdin Urii on 2009-01-26 05:10:03 UTC

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Creator: Nuzhdin Urii

Created: 2009-01-26 05:10:03 UTC

Size: 48.32 KB

patch

obsolete

>
>X.Org X Server 1.5.3
>Release Date: 5 November 2008
>X Protocol Version 11, Revision 0
>Build Operating System: Linux 2.6.28-gentoo i686 
>Current Operating System: Linux R2H 2.6.28-gentoo #19 Tue Jan 27 12:19:04 MSK 2009 i686
>Build Date: 08 January 2009  06:20:31PM
> 
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/var/log/Xorg.0.log", Time: Tue Jan 27 16:02:45 2009
>(==) Using config file: "/etc/X11/xorg.conf"
>(==) ServerLayout "Layout0"
>(**) |-->Screen "Screen0" (0)
>(**) |   |-->Monitor "Monitor0"
>(**) |   |-->Device "Device0"
>(**) |-->Input Device "touchscreen"
>(**) Option "AllowEmptyInput" "True"
>(==) Automatically adding devices
>(==) Automatically enabling devices
>(==) Including the default font path built-ins.
>(**) FontPath set to:
>	/usr/share/fonts/misc,
>	/usr/share/fonts/TTF,
>	/usr/share/fonts/OTF,
>	/usr/share/fonts/Type1,
>	/usr/share/fonts/100dpi,
>	/usr/share/fonts/75dpi,
>	built-ins
>(==) ModulePath set to "/usr/lib/xorg/modules"
>(II) Cannot locate a core keyboard device.
>(II) The server relies on HAL to provide the list of input devices.
>	If no devices become available, reconfigure HAL or disable AllowEmptyInput.
>(WW) Open ACPI failed (/var/run/acpid.socket) (Connection refused)
>(II) No APM support in BIOS or kernel
>(II) Loader magic: 0x81cfb80
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.4
>	X.Org Video Driver: 4.1
>	X.Org XInput driver : 2.1
>	X.Org Server Extension : 1.1
>	X.Org Font Renderer : 0.6
>(II) Loader running on linux
>(--) using VT number 7
>
>(--) PCI:*(0@0:2:0) Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller rev 4, Mem @ 0xfeb80000/0, 0xd0000000/0, 0xfeb40000/0, I/O @ 0x0000ec00/0
>(--) PCI: (0@0:2:1) Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller rev 4, Mem @ 0xfea80000/0
>(II) System resource ranges:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>(II) "extmod" will be loaded. This was enabled by default and also specified in the config file.
>(II) "dbe" will be loaded by default.
>(II) "glx" will be loaded. This was enabled by default and also specified in the config file.
>(II) "freetype" will be loaded. This was enabled by default and also specified in the config file.
>(II) "record" will be loaded by default.
>(II) "dri" will be loaded. This was enabled by default and also specified in the config file.
>(II) LoadModule: "glx"
>
>(II) Loading /usr/lib/xorg/modules/extensions//libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 1.5.3, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 1.1
>(==) AIGLX enabled
>(==) Exporting typical set of GLX visuals
>(II) Loading extension GLX
>(II) LoadModule: "dri"
>
>(II) Loading /usr/lib/xorg/modules/extensions//libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 1.5.3, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 1.1
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "vbe"
>
>(II) Loading /usr/lib/xorg/modules//libvbe.so
>(II) Module vbe: vendor="X.Org Foundation"
>	compiled for 1.5.3, module version = 1.1.0
>	ABI class: X.Org Video Driver, version 4.1
>(II) LoadModule: "extmod"
>
>(II) Loading /usr/lib/xorg/modules/extensions//libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 1.5.3, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 1.1
>(II) Loading extension SHAPE
>(II) Loading extension MIT-SUNDRY-NONSTANDARD
>(II) Loading extension BIG-REQUESTS
>(II) Loading extension SYNC
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XC-MISC
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-Misc
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension TOG-CUP
>(II) Loading extension Extended-Visual-Information
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "freetype"
>
>(II) Loading /usr/lib/xorg/modules/fonts//libfreetype.so
>(II) Module freetype: vendor="X.Org Foundation & the After X-TT Project"
>	compiled for 1.5.3, module version = 2.1.0
>	Module class: X.Org Font Renderer
>	ABI class: X.Org Font Renderer, version 0.6
>(II) Loading font FreeType
>(II) LoadModule: "dbe"
>
>(II) Loading /usr/lib/xorg/modules/extensions//libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 1.5.3, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 1.1
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "record"
>
>(II) Loading /usr/lib/xorg/modules/extensions//librecord.so
>(II) Module record: vendor="X.Org Foundation"
>	compiled for 1.5.3, module version = 1.13.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 1.1
>(II) Loading extension RECORD
>(II) LoadModule: "intel"
>
>(II) Loading /usr/lib/xorg/modules/drivers//intel_drv.so
>(II) Module intel: vendor="X.Org Foundation"
>	compiled for 1.5.3, module version = 2.6.99
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 4.1
>(II) LoadModule: "evtouch"
>
>(II) Loading /usr/lib/xorg/modules/input//evtouch_drv.so
>(II) Module evtouch: vendor="Kenan Esau"
>	compiled for 4.3.99.902, module version = 0.8.8
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 2.1
>(II) intel: Driver for Intel Integrated Graphics Chipsets: i810,
>	i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G,
>	E7221 (i915), 915GM, 945G, 945GM, 945GME, 965G, G35, 965Q, 946GZ,
>	965GM, 965GME/GLE, G33, Q35, Q33,
>	Mobile IntelÂ® GM45 Express Chipset,
>	Intel Integrated Graphics Device, G45/G43, Q45/Q43, G41
>(II) Primary Device is: PCI 00@00:02:0
>(II) resource ranges after xf86ClaimFixedResources() call:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>(II) resource ranges after probing:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B]
>	[5] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B]
>	[6] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B]
>	[7] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[8] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>	[9] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B]
>	[10] 0	0	0x000003c0 - 0x000003df (0x20) IS[B]
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>
>(II) Loading /usr/lib/xorg/modules//libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 1.5.3, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 4.1
>(**) intel(0): Depth 24, (--) framebuffer bpp 32
>(==) intel(0): RGB weight 888
>(==) intel(0): Default visual is TrueColor
>(**) intel(0): Option "ModeDebug" "true"
>(II) intel(0): Integrated Graphics Chipset: Intel(R) 915GM
>(--) intel(0): Chipset: "915GM"
>(--) intel(0): Linear framebuffer at 0xD0000000
>(--) intel(0): IO registers at addr 0xFEB80000
>(WW) intel(0): libpciaccess reported 0 rom size, guessing 64kB
>(==) intel(0): Using EXA for acceleration
>(II) intel(0): Hardware state on X startup:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x11a97828 (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh disabled, flex disabled, ep not present)
>(II) intel(0):               C0DRB0: 0x000f0401 (0x0401)
>(II) intel(0):               C0DRB1: 0x0000000f (0x000f)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x04000000 (0x0000)
>(II) intel(0):               C1DRB0: 0x05040302 (0x0302)
>(II) intel(0):               C1DRB1: 0x07060504 (0x0504)
>(II) intel(0):               C1DRB2: 0x09080706 (0x0706)
>(II) intel(0):               C1DRB3: 0x0b0a0908 (0x0908)
>(II) intel(0):              C0DRA01: 0x01000400 (0x0400)
>(II) intel(0):              C0DRA23: 0x02000100 (0x0100)
>(II) intel(0):              C1DRA01: 0x0d0c0b0a (0x0b0a)
>(II) intel(0):              C1DRA23: 0x0f0e0d0c (0x0d0c)
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00800080 (vga0 p1 = 2, p2 = 4, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) intel(0):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0xc0008300 (enabled, pipe B, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) intel(0):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x025907d1
>(II) intel(0):        PP_OFF_DELAYS: 0x01f507d1
>(II) intel(0):           PP_DIVISOR: 0x00270f05
>(II) intel(0):         PFIT_CONTROL: 0x00002668
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEASTAT: 0x00000000 (status:)
>(II) intel(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0x04800000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x49000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000280 (640 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x018f02cf (720, 400)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x031f01df (800, 480)
>(II) intel(0):            PIPEBSTAT: 0x00000202 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPB0: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x98200000 (enabled, non-dvo, default clock, LVDS mode, p1 = 6, p2 = 14)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x0383031f (800 active, 900 total)
>(II) intel(0):             HBLANK_B: 0x0383031f (800 start, 900 end)
>(II) intel(0):              HSYNC_B: 0x03870327 (808 start, 904 end)
>(II) intel(0):             VTOTAL_B: 0x01f301df (480 active, 500 total)
>(II) intel(0):             VBLANK_B: 0x01f301df (480 start, 500 end)
>(II) intel(0):              VSYNC_B: 0x01e301e1 (482 start, 484 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00800080
>(II) intel(0):             VGACNTRL: 0x21c4008e (enabled)
>(II) intel(0):               TV_CTL: 0x00000000
>(II) intel(0):               TV_DAC: 0x70000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x20000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):        FENCE START 0: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 0: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 1: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 1: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 2: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 2: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 3: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 3: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 4: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 4: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 5: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 5: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 6: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 6: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 7: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 7: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 8: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 8: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 9: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 9: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 10: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 10: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 11: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 11: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 12: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 12: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 13: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 13: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 14: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 14: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 15: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 15: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): pipe B dot 26971 n 3 m1 20 m2 6 p1 6 p2 14
>(II) intel(0): DumpRegsEnd
>(II) intel(0): 2 display pipes available.
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"
>(II) Module "ddc" already built-in
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"
>(II) Module "i2c" already built-in
>(II) intel(0): Output VGA using monitor section Monitor0
>(II) intel(0): Output LVDS has no monitor section
>(II) intel(0): I2C bus "LVDSDDC_C" initialized.
>(II) intel(0): Attempting to determine panel fixed mode.
>(II) intel(0): I2C device "LVDSDDC_C:ddc2" registered at address 0xA0.
>(II) intel(0): I2C device "LVDSDDC_C:ddc2" removed.
>(II) intel(0): found backlight control method /sys/class/backlight/asus-laptop
>(II) intel(0): Output TV has no monitor section
>(II) intel(0): Resizable framebuffer: not available (1 3)
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 491 520 -hsync -vsync (37.9 kHz)
>(II) intel(0): chosen: dotclock 31500 vco 2520000 ((m 105, m1 17, m2 8), n 2, (p 80, p1 8, p2 10))
>(II) intel(0): I2C bus "CRTDDC_A" initialized.
>(II) intel(0): I2C bus "CRTDDC_A" removed.
>(II) intel(0): EDID for output VGA
>(II) intel(0): LID switch detect open with SWF14 0x       0
>(II) intel(0): I2C device "LVDSDDC_C:ddc2" registered at address 0xA0.
>(II) intel(0): I2C device "LVDSDDC_C:ddc2" removed.
>(II) intel(0): EDID for output LVDS
>(II) intel(0): Not using mode "2303x1546" (width too large for virtual size)
>(II) intel(0): Printing probed modes for output LVDS
>(II) intel(0): Modeline "2048x1536"x85.0  388.04  2048 2216 2440 2832  1536 1537 1540 1612 -hsync +vsync (137.0 kHz)
>(II) intel(0): Modeline "2048x1536"x75.0  340.48  2048 2216 2440 2832  1536 1537 1540 1603 -hsync +vsync (120.2 kHz)
>(II) intel(0): Modeline "2048x1536"x60.0  266.95  2048 2200 2424 2800  1536 1537 1540 1589 -hsync +vsync (95.3 kHz)
>(II) intel(0): Modeline "1920x1440"x85.0  341.35  1920 2072 2288 2656  1440 1441 1444 1512 -hsync +vsync (128.5 kHz)
>(II) intel(0): Modeline "1920x1440"x75.0  297.00  1920 2064 2288 2640  1440 1441 1444 1500 -hsync +vsync (112.5 kHz)
>(II) intel(0): Modeline "1920x1440"x60.0  234.00  1920 2048 2256 2600  1440 1441 1444 1500 -hsync +vsync (90.0 kHz)
>(II) intel(0): Modeline "1856x1392"x75.0  288.00  1856 1984 2208 2560  1392 1393 1396 1500 -hsync +vsync (112.5 kHz)
>(II) intel(0): Modeline "1856x1392"x60.0  218.30  1856 1952 2176 2528  1392 1393 1396 1439 -hsync +vsync (86.4 kHz)
>(II) intel(0): Modeline "1792x1344"x75.0  261.00  1792 1888 2104 2456  1344 1345 1348 1417 -hsync +vsync (106.3 kHz)
>(II) intel(0): Modeline "1792x1344"x60.0  204.80  1792 1920 2120 2448  1344 1345 1348 1394 -hsync +vsync (83.7 kHz)
>(II) intel(0): Modeline "1600x1200"x85.0  229.50  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (106.2 kHz)
>(II) intel(0): Modeline "1600x1200"x75.0  202.50  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (93.8 kHz)
>(II) intel(0): Modeline "1600x1200"x70.0  189.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (87.5 kHz)
>(II) intel(0): Modeline "1600x1200"x65.0  175.50  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (81.2 kHz)
>(II) intel(0): Modeline "1600x1200"x60.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz)
>(II) intel(0): Modeline "1400x1050"x74.8  155.80  1400 1464 1784 1912  1050 1052 1064 1090 +hsync +vsync (81.5 kHz)
>(II) intel(0): Modeline "1400x1050"x60.0  122.00  1400 1488 1640 1880  1050 1052 1064 1082 +hsync +vsync (64.9 kHz)
>(II) intel(0): Modeline "1280x1024"x85.0  157.50  1280 1344 1504 1728  1024 1025 1028 1072 +hsync +vsync (91.1 kHz)
>(II) intel(0): Modeline "1280x1024"x75.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz)
>(II) intel(0): Modeline "1280x1024"x60.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz)
>(II) intel(0): Modeline "1280x960"x85.0  148.50  1280 1344 1504 1728  960 961 964 1011 +hsync +vsync (85.9 kHz)
>(II) intel(0): Modeline "1280x960"x60.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz)
>(II) intel(0): Modeline "1152x864"x75.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz)
>(II) intel(0): Modeline "1024x768"x85.0   94.50  1024 1072 1168 1376  768 769 772 808 +hsync +vsync (68.7 kHz)
>(II) intel(0): Modeline "1024x768"x75.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz)
>(II) intel(0): Modeline "1024x768"x70.1   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz)
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) intel(0): Modeline "832x624"x74.6   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz)
>(II) intel(0): Modeline "800x600"x85.1   56.30  800 832 896 1048  600 601 604 631 +hsync +vsync (53.7 kHz)
>(II) intel(0): Modeline "800x600"x72.2   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz)
>(II) intel(0): Modeline "800x600"x75.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz)
>(II) intel(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz)
>(II) intel(0): Modeline "640x480"x85.0   36.00  640 696 752 832  480 481 484 509 -hsync -vsync (43.3 kHz)
>(II) intel(0): Modeline "640x480"x72.8   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz)
>(II) intel(0): Modeline "640x480"x75.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz)
>(II) intel(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): Modeline "720x400"x85.0   35.50  720 756 828 936  400 401 404 446 -hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x400"x85.1   31.50  640 672 736 832  400 401 404 445 -hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x350"x85.1   31.50  640 672 736 832  350 382 385 445 +hsync -vsync (37.9 kHz)
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  107.52  1280 1368 1496 1712  1024 1027 1034 1104 (62.8 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  108.00  1280 1368 1496 1712  1024 1027 1034 1104 (63.1 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>(II) intel(0): Detected Composite TV connection
>(II) intel(0): Not using default mode "640x350" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x400" (vrefresh out of range)
>(II) intel(0): Not using default mode "720x400" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (vrefresh out of range)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) intel(0): Not using default mode "1152x864" (vrefresh out of range)
>(II) intel(0): Not using default mode "1280x960" (vrefresh out of range)
>(II) intel(0): Not using default mode "1280x960" (vrefresh out of range)
>(II) intel(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) intel(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) intel(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) intel(0): Not using default mode "1792x1344" (vrefresh out of range)
>(II) intel(0): Not using default mode "1792x1344" (vrefresh out of range)
>(II) intel(0): Not using default mode "1856x1392" (vrefresh out of range)
>(II) intel(0): Not using default mode "1856x1392" (vrefresh out of range)
>(II) intel(0): Not using default mode "1920x1440" (vrefresh out of range)
>(II) intel(0): Not using default mode "1920x1440" (vrefresh out of range)
>(II) intel(0): Not using default mode "832x624" (vrefresh out of range)
>(II) intel(0): Not using default mode "1400x1050" (vrefresh out of range)
>(II) intel(0): Not using default mode "1400x1050" (vrefresh out of range)
>(II) intel(0): Not using default mode "1920x1440" (vrefresh out of range)
>(II) intel(0): Not using default mode "2048x1536" (vrefresh out of range)
>(II) intel(0): Not using default mode "2048x1536" (vrefresh out of range)
>(II) intel(0): Not using default mode "2048x1536" (vrefresh out of range)
>(II) intel(0): Printing probed modes for output TV
>(II) intel(0): Modeline "1024x768"x30.0   26.89  1024 1025 1088 1120  768 769 800 801 (24.0 kHz)
>(II) intel(0): Modeline "800x600"x30.0   17.00  800 801 864 896  600 601 632 633 (19.0 kHz)
>(II) intel(0): Modeline "848x480"x30.0   14.51  848 849 912 944  480 481 512 513 (15.4 kHz)
>(II) intel(0): Modeline "640x480"x30.0   11.31  640 641 704 736  480 481 512 513 (15.4 kHz)
>(II) intel(0): Output VGA disconnected
>(II) intel(0): Output LVDS connected
>(II) intel(0): Output TV connected
>(II) intel(0): Using fuzzy aspect match for initial modes
>(II) intel(0): Output LVDS using initial mode 1024x768
>(II) intel(0): Output TV using initial mode 1024x768
>(II) intel(0): detected 256 kB GTT.
>(II) intel(0): detected 16124 kB stolen memory.
>(==) intel(0): video overlay key set to 0x101fe
>(==) intel(0): Using gamma correction (1.0, 1.0, 1.0)
>(==) intel(0): DPI set to (96, 96)
>(II) Loading sub module "fb"
>(II) LoadModule: "fb"
>
>(II) Loading /usr/lib/xorg/modules//libfb.so
>(II) Module fb: vendor="X.Org Foundation"
>	compiled for 1.5.3, module version = 1.0.0
>	ABI class: X.Org ANSI C Emulation, version 0.4
>(II) Loading sub module "exa"
>(II) LoadModule: "exa"
>
>(II) Loading /usr/lib/xorg/modules//libexa.so
>(II) Module exa: vendor="X.Org Foundation"
>	compiled for 1.5.3, module version = 2.4.0
>	ABI class: X.Org Video Driver, version 4.1
>(II) Loading sub module "ramdac"
>(II) LoadModule: "ramdac"
>(II) Module "ramdac" already built-in
>(II) intel(0): Comparing regs from server start up to After PreInit
>(WW) intel(0): Register 0x61200 (PP_STATUS) changed from 0xc0000008 to 0xd0000009
>(WW) intel(0): PP_STATUS before: on, ready, sequencing idle
>(WW) intel(0): PP_STATUS after: on, ready, sequencing on
>(WW) intel(0): Register 0x70024 (PIPEASTAT) changed from 0x00000000 to 0x00000207
>(WW) intel(0): PIPEASTAT before: status:
>(WW) intel(0): PIPEASTAT after: status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS
>(WW) intel(0): Register 0x71024 (PIPEBSTAT) changed from 0x00000202 to 0x80000242
>(WW) intel(0): PIPEBSTAT before: status: VSYNC_INT_STATUS VBLANK_INT_STATUS
>(WW) intel(0): PIPEBSTAT after: status: FIFO_UNDERRUN VSYNC_INT_STATUS LBLC_EVENT_STATUS VBLANK_INT_STATUS
>(==) Depth 24 pixmap format is 32 bpp
>(II) do I need RAC?  No, I don't.
>(II) resource ranges after preInit:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B](OprD)
>	[5] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD)
>	[6] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B](OprD)
>	[7] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[8] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>	[9] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B](OprU)
>	[10] 0	0	0x000003c0 - 0x000003df (0x20) IS[B](OprU)
>(II) intel(0): Kernel reported 172544 total, 1 used
>(II) intel(0): I830CheckAvailableMemory: 690172 kB available
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 10, (OK)
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 10, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 10, (OK)
>drmOpenByBusid: drmOpenMinor returns 10
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(II) [drm] DRM interface version 1.3
>(II) [drm] DRM open master succeeded.
>(II) intel(0): [drm] Using the DRM lock SAREA also for drawables.
>(II) intel(0): [drm] framebuffer mapped by ddx driver
>(II) intel(0): [drm] added 1 reserved context for kernel
>(II) intel(0): X context handle = 0x1
>(II) intel(0): [drm] installed DRM signal handler
>(**) intel(0): Framebuffer compression enabled
>(**) intel(0): Tiling enabled
>(==) intel(0): VideoRam: 262144 KB
>(II) intel(0): Attempting memory allocation with tiled buffers.
>(II) intel(0): Tiled allocation successful.
>(II) intel(0): [drm] Registers = 0xfeb80000
>(II) intel(0): [drm] Initialized kernel agp heap manager, 33554432
>(II) intel(0): [dri] visual configs initialized
>(II) intel(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000
>(II) EXA(0): Offscreen pixmap area of 50331648 bytes
>(II) EXA(0): Driver registered support for the following operations:
>(II)         Solid
>(II)         Copy
>(II)         Composite (RENDER acceleration)
>(==) intel(0): Backing store disabled
>(==) intel(0): Silken mouse enabled
>(II) intel(0): Initializing HW Cursor
>(II) intel(0): [DRI] installation complete
>(II) intel(0): xf86BindGARTMemory: bind key 0 at 0x0a9f4000 (pgoffset 43508)
>(II) intel(0): xf86BindGARTMemory: bind key 1 at 0x0d9f4000 (pgoffset 55796)
>(II) intel(0): Fixed memory allocation layout:
>(II) intel(0): 0x00000000-0x005fffff: compressed frame buffer (6144 kB, 0x000000002f000000 physical
>)
>(II) intel(0): 0x00600000-0x00600fff: compressed ll buffer (4 kB, 0x000000002f600000 physical
>)
>(II) intel(0): 0x00601000-0x0060afff: HW cursors (40 kB, 0x000000002f601000 physical
>)
>(II) intel(0): 0x0060b000-0x0060bfff: overlay registers (4 kB, 0x000000002f60b000 physical
>)
>(II) intel(0): 0x00fbf000:            end of stolen memory
>(II) intel(0): 0x00fbf000-0x0a9f3fff: DRI memory manager (157908 kB)
>(II) intel(0): 0x0a9f4000-0x0d9f3fff: exa offscreen (49152 kB)
>(II) intel(0): 0x0d9f4000-0x0f9f3fff: classic textures (32768 kB)
>(II) intel(0): 0x10000000:            end of aperture
>(II) intel(0): BO memory allocation layout:
>(II) intel(0): 0x00fbf000:            start of memory manager
>(II) intel(0): 0x01000000-0x01ffffff: depth buffer (16384 kB) X tiled
>(II) intel(0): 0x02000000-0x02ffffff: back buffer (16384 kB) X tiled
>(II) intel(0): 0x03000000-0x03ffffff: front buffer (16384 kB) X tiled
>(II) intel(0): 0x0a9f4000:            end of memory manager
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "1024x768"x30.0   26.89  1024 1025 1088 1120  768 769 800 801 (24.0 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "1024x768"x30.0  108.00  1024 1025 1088 1120  768 769 800 801 (24.0 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>
>Fatal server error:
>Couldn't find PLL settings for mode!
>
>(II) intel(0): Comparing regs from server start up to After LeaveVT
>(WW) intel(0): Register 0x61200 (PP_STATUS) changed from 0xc0000008 to 0xd0000009
>(WW) intel(0): PP_STATUS before: on, ready, sequencing idle
>(WW) intel(0): PP_STATUS after: on, ready, sequencing on
>(WW) intel(0): Register 0x70024 (PIPEASTAT) changed from 0x00000000 to 0x00000203
>(WW) intel(0): PIPEASTAT before: status:
>(WW) intel(0): PIPEASTAT after: status: VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS
>(WW) intel(0): Register 0x71024 (PIPEBSTAT) changed from 0x00000202 to 0x80000242
>(WW) intel(0): PIPEBSTAT before: status: VSYNC_INT_STATUS VBLANK_INT_STATUS
>(WW) intel(0): PIPEBSTAT after: status: FIFO_UNDERRUN VSYNC_INT_STATUS LBLC_EVENT_STATUS VBLANK_INT_STATUS
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x11a97828 (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh disabled, flex disabled, ep not present)
>(II) intel(0):               C0DRB0: 0x000f0401 (0x0401)
>(II) intel(0):               C0DRB1: 0x0000000f (0x000f)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x04000000 (0x0000)
>(II) intel(0):               C1DRB0: 0x05040302 (0x0302)
>(II) intel(0):               C1DRB1: 0x07060504 (0x0504)
>(II) intel(0):               C1DRB2: 0x09080706 (0x0706)
>(II) intel(0):               C1DRB3: 0x0b0a0908 (0x0908)
>(II) intel(0):              C0DRA01: 0x01000400 (0x0400)
>(II) intel(0):              C0DRA23: 0x02000100 (0x0100)
>(II) intel(0):              C1DRA01: 0x0d0c0b0a (0x0b0a)
>(II) intel(0):              C1DRA23: 0x0f0e0d0c (0x0d0c)
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00800080 (vga0 p1 = 2, p2 = 4, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) intel(0):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0xc0008300 (enabled, pipe B, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) intel(0):            PP_STATUS: 0xd0000009 (on, ready, sequencing on)
>(II) intel(0):         PP_ON_DELAYS: 0x025907d1
>(II) intel(0):        PP_OFF_DELAYS: 0x01f507d1
>(II) intel(0):           PP_DIVISOR: 0x00270f05
>(II) intel(0):         PFIT_CONTROL: 0x00002668
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEASTAT: 0x00000203 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0x04800000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x49000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000280 (640 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x018f02cf (720, 400)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x031f01df (800, 480)
>(II) intel(0):            PIPEBSTAT: 0x80000242 (status: FIFO_UNDERRUN VSYNC_INT_STATUS LBLC_EVENT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPB0: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x98200000 (enabled, non-dvo, default clock, LVDS mode, p1 = 6, p2 = 14)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x0383031f (800 active, 900 total)
>(II) intel(0):             HBLANK_B: 0x0383031f (800 start, 900 end)
>(II) intel(0):              HSYNC_B: 0x03870327 (808 start, 904 end)
>(II) intel(0):             VTOTAL_B: 0x01f301df (480 active, 500 total)
>(II) intel(0):             VBLANK_B: 0x01f301df (480 start, 500 end)
>(II) intel(0):              VSYNC_B: 0x01e301e1 (482 start, 484 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00800080
>(II) intel(0):             VGACNTRL: 0x21c4008e (enabled)
>(II) intel(0):               TV_CTL: 0x00000000
>(II) intel(0):               TV_DAC: 0x70000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x20000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):        FENCE START 0: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 0: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 1: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 1: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 2: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 2: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 3: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 3: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 4: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 4: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 5: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 5: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 6: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 6: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 7: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 7: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 8: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 8: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):        FENCE START 9: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):          FENCE END 9: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 10: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 10: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 11: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 11: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 12: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 12: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 13: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 13: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 14: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 14: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0):       FENCE START 15: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II) intel(0):         FENCE END 15: 0xffffffff (                                   0xfffff000 end)
>(II) intel(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): pipe B dot 26971 n 3 m1 20 m2 6 p1 6 p2 14
>(II) intel(0): DumpRegsEnd
>(II) intel(0): xf86UnbindGARTMemory: unbind key 0
>(II) intel(0): xf86UnbindGARTMemory: unbind key 1

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Attachments on bug 19460: 21981 | 21983 | 22011 | 22012 | 22244 | 22511 | 22660 | 22661 | 22746 | 22870 | 22890 | 22908 | 22932 | 22972 | 22980 | 23000 | 23145 | 25420 | 25750

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