Attachment 21541 Details for Bug 19233 – Xorg.0.log

Xorg.0.log

Xorg.0.log (text/plain), 77.43 KB, created by Fatih Aşıcı on 2008-12-28 22:22:23 UTC

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Creator: Fatih Aşıcı

Created: 2008-12-28 22:22:23 UTC

Size: 77.43 KB

patch

obsolete

>
>This is a pre-release version of the X server from The X.Org Foundation.
>It is not supported in any way.
>Bugs may be filed in the bugzilla at http://bugs.freedesktop.org/.
>Select the "xorg" product for bugs you find in this release.
>Before reporting bugs in pre-release versions please check the
>latest version in the X.Org Foundation git repository.
>See http://wiki.x.org/wiki/GitPage for git access instructions.
>
>X.Org X Server 1.5.99.3
>Release Date: (unreleased)
>X Protocol Version 11, Revision 0
>Build Operating System: Pardus TÃBÄ°TAK, UEKAE
>Current Operating System: Linux inspiron 2.6.28_rc9-114 #1 SMP Thu Dec 25 01:42:58 EET 2008 i686
>Build Date: 19 December 2008  12:02:24AM
> 
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/var/log/Xorg.0.log", Time: Mon Dec 29 08:14:49 2008
>(==) Using config file: "/etc/X11/xorg.conf"
>(==) No Layout section.  Using the first Screen section.
>(==) No screen section available. Using defaults.
>(**) |-->Screen "Default Screen Section" (0)
>(**) |   |-->Monitor "<default monitor>"
>(==) No device specified for screen "Default Screen Section".
>	Using the first device section listed.
>(**) |   |-->Device "VideoCard"
>(==) No monitor specified for screen "Default Screen Section".
>	Using a default monitor configuration.
>(**) Option "DontZap" "off"
>(**) Option "VTSysReq" "on"
>(==) Automatically adding devices
>(==) Automatically enabling devices
>(**) VTSysReq enabled
>(==) No FontPath specified.  Using compiled-in default.
>(==) FontPath set to:
>	catalogue:/etc/X11/fontpath.d,
>	built-ins
>(==) ModulePath set to "/usr/lib/xorg/modules"
>(II) Cannot locate a core pointer device.
>(II) Cannot locate a core keyboard device.
>(II) The server relies on HAL to provide the list of input devices.
>	If no devices become available, reconfigure HAL or disable AllowEmptyInput.
>(II) Loader magic: 0x1a60
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.4
>	X.Org Video Driver: 5.0
>	X.Org XInput driver : 4.0
>	X.Org Server Extension : 2.0
>(II) Loader running on linux
>(++) using VT number 1
>
>(--) PCI:*(0@0:2:0) Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller rev 12, Mem @ 0xfea00000/0, 0xe0000000/0, I/O @ 0x0000eff8/0
>(--) PCI: (0@0:2:1) Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller rev 12, Mem @ 0xfeb00000/0
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) System resource ranges:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>(II) LoadModule: "extmod"
>(II) Loading /usr/lib/xorg/modules/extensions//libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 1.5.99.3, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "dbe"
>(II) Loading /usr/lib/xorg/modules/extensions//libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 1.5.99.3, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "glx"
>(II) Loading /usr/lib/xorg/modules/extensions//libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 1.5.99.3, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(==) AIGLX enabled
>(==) Exporting typical set of GLX visuals
>(II) Loading extension GLX
>(II) LoadModule: "dri"
>(II) Loading /usr/lib/xorg/modules/extensions//libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 1.5.99.3, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "dri2"
>(II) Loading /usr/lib/xorg/modules/extensions//libdri2.so
>(II) Module dri2: vendor="X.Org Foundation"
>	compiled for 1.5.99.3, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension DRI2
>(II) LoadModule: "intel"
>(II) Loading /usr/lib/xorg/modules/drivers//intel_drv.so
>(II) Module intel: vendor="X.Org Foundation"
>	compiled for 1.5.99.3, module version = 2.6.99
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 5.0
>(II) intel: Driver for Intel Integrated Graphics Chipsets: i810,
>	i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G,
>	E7221 (i915), 915GM, 945G, 945GM, 945GME, 965G, G35, 965Q, 946GZ,
>	965GM, 965GME/GLE, G33, Q35, Q33,
>	Mobile IntelÂ® GM45 Express Chipset,
>	Intel Integrated Graphics Device, G45/G43, Q45/Q43, G41
>(II) Primary Device is: PCI 00@00:02:0
>(II) resource ranges after xf86ClaimFixedResources() call:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>(II) resource ranges after probing:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B]
>	[5] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B]
>	[6] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B]
>	[7] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[8] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>	[9] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B]
>	[10] 0	0	0x000003c0 - 0x000003df (0x20) IS[B]
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>(II) Loading /usr/lib/xorg/modules//libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 1.5.99.3, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 5.0
>(II) intel(0): Creating default Display subsection in Screen section
>	"Default Screen Section" for depth/fbbpp 24/32
>(==) intel(0): Depth 24, (--) framebuffer bpp 32
>(==) intel(0): RGB weight 888
>(==) intel(0): Default visual is TrueColor
>(**) intel(0): Option "AccelMethod" "UXA"
>(**) intel(0): Option "ModeDebug" "on"
>(II) intel(0): Integrated Graphics Chipset: Intel(R) 965GM
>(--) intel(0): Chipset: "965GM"
>(--) intel(0): Linear framebuffer at 0xE0000000
>(--) intel(0): IO registers at addr 0xFEA00000
>(WW) intel(0): libpciaccess reported 0 rom size, guessing 64kB
>(**) intel(0): Using UXA for acceleration
>(II) intel(0): Hardware state on X startup:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>(II) intel(0):               C0DRB0: 0x000f0002 (0x0002)
>(II) intel(0):               C0DRB1: 0x0000000f (0x000f)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x00c00000 (0x0000)
>(II) intel(0):               C1DRB0: 0x17cbe000 (0xe000)
>(II) intel(0):               C1DRB1: 0x000017cb (0x17cb)
>(II) intel(0):               C1DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB3: 0x00000000 (0x0000)
>(II) intel(0):              C0DRA01: 0x000300c0 (0x00c0)
>(II) intel(0):              C0DRA23: 0x000c0003 (0x0003)
>(II) intel(0):              C1DRA01: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA23: 0x00000000 (0x0000)
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006800
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000ca9 (clock gates disabled: DPOUNIT DPBUNIT VRUNIT OVFUNIT OVRUNIT OVLUNIT)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x0008001c (disabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x3f8f0f0f
>(II) intel(0):               DSPFW2: 0x00000f0f
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0xc2308300 (enabled, pipe B, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x0008001c (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):                 DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000003 (power target: on)
>(II) intel(0):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x012c07d0
>(II) intel(0):        PP_OFF_DELAYS: 0x012c0bc0
>(II) intel(0):           PP_DIVISOR: 0x003e7f06
>(II) intel(0):         PFIT_CONTROL: 0xa0000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x0f5c0ccd
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000400
>(II) intel(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x00000000 (disabled, inactive)
>(II) intel(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEASTAT: 0x00000000 (status:)
>(II) intel(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0x04800c00 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II) intel(0):            DPLL_A_MD: 0x00000303
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x95000000 (enabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000800 (2048 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0xc0000000 (enabled, active)
>(II) intel(0):             PIPEBSRC: 0x03ff02ff (1024, 768)
>(II) intel(0):            PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPB0: 0x00010f08 (n = 1, m1 = 15, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x98046a00 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 3, p2 = 14)
>(II) intel(0):            DPLL_B_MD: 0x00000003
>(II) intel(0):             HTOTAL_B: 0x05e704ff (1280 active, 1512 total)
>(II) intel(0):             HBLANK_B: 0x05e704ff (1280 start, 1512 end)
>(II) intel(0):              HSYNC_B: 0x056f053f (1344 start, 1392 end)
>(II) intel(0):             VTOTAL_B: 0x033f031f (800 active, 832 total)
>(II) intel(0):             VBLANK_B: 0x033f031f (800 start, 832 end)
>(II) intel(0):              VSYNC_B: 0x03280322 (803 start, 809 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0xa2c4008e (disabled)
>(II) intel(0):               TV_CTL: 0x000c00c0
>(II) intel(0):               TV_DAC: 0x70000000
>(II) intel(0):             TV_CSC_Y: 0x0332012d
>(II) intel(0):            TV_CSC_Y2: 0x07d30104
>(II) intel(0):             TV_CSC_U: 0x0733052d
>(II) intel(0):            TV_CSC_U2: 0x05c70200
>(II) intel(0):             TV_CSC_V: 0x0340030c
>(II) intel(0):            TV_CSC_V2: 0x06d00200
>(II) intel(0):         TV_CLR_KNOBS: 0x00404000
>(II) intel(0):         TV_CLR_LEVEL: 0x010b00e1
>(II) intel(0):           TV_H_CTL_1: 0x00400359
>(II) intel(0):           TV_H_CTL_2: 0x80480022
>(II) intel(0):           TV_H_CTL_3: 0x007c0344
>(II) intel(0):           TV_V_CTL_1: 0x00f01415
>(II) intel(0):           TV_V_CTL_2: 0x00060607
>(II) intel(0):           TV_V_CTL_3: 0x80120001
>(II) intel(0):           TV_V_CTL_4: 0x000900f0
>(II) intel(0):           TV_V_CTL_5: 0x000a00f0
>(II) intel(0):           TV_V_CTL_6: 0x000900f0
>(II) intel(0):           TV_V_CTL_7: 0x000a00f0
>(II) intel(0):          TV_SC_CTL_1: 0xc1710087
>(II) intel(0):          TV_SC_CTL_2: 0x6b405140
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00360024
>(II) intel(0):          TV_WIN_SIZE: 0x02640198
>(II) intel(0):      TV_FILTER_CTL_1: 0x8000085e
>(II) intel(0):      TV_FILTER_CTL_2: 0x00028283
>(II) intel(0):      TV_FILTER_CTL_3: 0x00014141
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0xb1403000
>(II) intel(0):         TV_H_LUMA_59: 0x0000b060
>(II) intel(0):        TV_H_CHROMA_0: 0xb1403000
>(II) intel(0):       TV_H_CHROMA_59: 0x0000b060
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x20000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000044
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):        FENCE START 0: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 0: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 1: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 1: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 2: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 2: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 3: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 3: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 4: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 4: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 5: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 5: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 6: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 6: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 7: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 7: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 8: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 8: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 9: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 9: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 10: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 10: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 11: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 11: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 12: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 12: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 13: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 13: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 14: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 14: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 15: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 15: 0x00000000 (                                   0x00000000 end)
>(II) intel(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): SDVO phase shift 5 out of range -- probobly not an issue.
>(II) intel(0): pipe B dot 75396 n 1 m1 15 m2 8 p1 3 p2 14
>(II) intel(0): DumpRegsEnd
>(II) intel(0): 2 display pipes available.
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"
>(II) Module "ddc" already built-in
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"
>(II) Module "i2c" already built-in
>(II) intel(0): Output VGA has no monitor section
>(II) intel(0): Output LVDS has no monitor section
>(II) intel(0): I2C bus "LVDSDDC_C" initialized.
>(II) intel(0): Attempting to determine panel fixed mode.
>(II) intel(0): I2C device "LVDSDDC_C:E-EDID segment register" registered at address 0x60.
>(II) intel(0): I2C device "LVDSDDC_C:ddc2" registered at address 0xA0.
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): found backlight control method /sys/class/backlight/acpi_video0
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOB" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOB:SDVO Controller B" registered at address 0x70.
>(II) intel(0): I2C bus "SDVOB DDC Bus" initialized.
>(II) intel(0): SDVOB: W: 02                         (SDVO_CMD_GET_DEVICE_CAPS)
>(II) intel(0): SDVOB: R: 04 AE 00 02 01 01 01 00 (Success)
>(II) intel(0): SDVOB: W: 9D                         (SDVO_CMD_GET_SUPP_ENCODE)
>(II) intel(0): SDVOB: R: 10 12                   (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 9E                         (SDVO_CMD_GET_ENCODE)
>(II) intel(0): SDVOB: R: 00                      (Success)
>(II) intel(0): Output TMDS-1 has no monitor section
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 1D                         (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE)
>(II) intel(0): SDVOB: R: C4 09 74 40             (Success)
>(II) intel(0): SDVOB: device VID/DID: 04:AE.00, clock range 25.0MHz - 165.0MHz
>(II) intel(0): SDVOB: 1 input channel
>(II) intel(0): SDVOB: TMDS0 output reported
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOC" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" registered at address 0x72.
>(II) intel(0): No SDVO device found on SDVOC
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" removed.
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOC" removed.
>(II) intel(0): Output TV has no monitor section
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): Current clock rate multiplier: 1
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): EDID for output VGA
>(II) intel(0): LID switch detect open with ACPI button
>(II) intel(0): EDID for output LVDS
>(II) intel(0): Manufacturer: LPL  Model: 301  Serial#: 0
>(II) intel(0): Year: 2007  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 33  vert.: 21
>(II) intel(0): Gamma: 2.20
>(II) intel(0): No DPMS capabilities specified
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.600 redY: 0.351   greenX: 0.324 greenY: 0.554
>(II) intel(0): blueX: 0.153 blueY: 0.145   whiteX: 0.312 whiteY: 0.328
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0):  W654G154W01
>(II) intel(0):  $2=Eh§ÿ
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff00320c010300000000
>(II) intel(0): 	00110103802115780ab3409959538d27
>(II) intel(0): 	25505400000001010101010101010101
>(II) intel(0): 	0101010101017e1d00e8502020304030
>(II) intel(0): 	36004bcf100000197e1d00e850202030
>(II) intel(0): 	403036004bcf10000000000000fe0057
>(II) intel(0): 	36353447803135345730310a000000fe
>(II) intel(0): 	0024323d45688ba7ff01010a202000a1
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing probed modes for output LVDS
>(II) intel(0): Modeline "1280x800"x60.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  107.52  1280 1368 1496 1712  1024 1027 1034 1104 (62.8 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  108.00  1280 1368 1496 1712  1024 1027 1034 1104 (63.1 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>(II) intel(0): No TV connection detected
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): EDID for output TV
>(II) intel(0): Output VGA disconnected
>(II) intel(0): Output LVDS connected
>(II) intel(0): Output TMDS-1 disconnected
>(II) intel(0): Output TV disconnected
>(II) intel(0): Using exact sizes for initial modes
>(II) intel(0): Output LVDS using initial mode 1280x800
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 00 00 00 00 00 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Not supported)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 00 00 00 00 00 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 15 00 00 00 00 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): detected 512 kB GTT.
>(II) intel(0): detected 7676 kB stolen memory.
>(==) intel(0): video overlay key set to 0x101fe
>(==) intel(0): Will not try to enable page flipping
>(==) intel(0): Triple buffering disabled
>(==) intel(0): Using gamma correction (1.0, 1.0, 1.0)
>(==) intel(0): DPI set to (96, 96)
>(II) Loading sub module "fb"
>(II) LoadModule: "fb"
>(II) Loading /usr/lib/xorg/modules//libfb.so
>(II) Module fb: vendor="X.Org Foundation"
>	compiled for 1.5.99.3, module version = 1.0.0
>	ABI class: X.Org ANSI C Emulation, version 0.4
>(II) Loading sub module "ramdac"
>(II) LoadModule: "ramdac"
>(II) Module "ramdac" already built-in
>(II) intel(0): Comparing regs from server start up to After PreInit
>(WW) intel(0): Register 0x61200 (PP_STATUS) changed from 0xc0000008 to 0xd0000009
>(WW) intel(0): PP_STATUS before: on, ready, sequencing idle
>(WW) intel(0): PP_STATUS after: on, ready, sequencing on
>(WW) intel(0): Register 0x71024 (PIPEBSTAT) changed from 0x00000206 to 0x00000000
>(WW) intel(0): PIPEBSTAT before: status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS
>(WW) intel(0): PIPEBSTAT after: status:
>(==) Depth 24 pixmap format is 32 bpp
>(II) do I need RAC?  No, I don't.
>(II) resource ranges after preInit:
>	[0] -1	0	0xffffffff - 0xffffffff (0x1) MX[B]
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B](OprD)
>	[5] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD)
>	[6] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B](OprD)
>	[7] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[8] -1	0	0x00000000 - 0x00000000 (0x1) IX[B]
>	[9] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B](OprU)
>	[10] 0	0	0x000003c0 - 0x000003df (0x20) IS[B](OprU)
>(II) intel(0): Kernel reported 488960 total, 1 used
>(II) intel(0): I830CheckAvailableMemory: 1955836 kB available
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 11, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 11, (OK)
>drmOpenByBusid: drmOpenMinor returns 11
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(II) intel(0): [DRI2] Setup complete
>(**) intel(0): Framebuffer compression disabled
>(**) intel(0): Tiling enabled
>(==) intel(0): VideoRam: 262144 KB
>(II) intel(0): Attempting memory allocation with tiled buffers.
>(II) intel(0): Tiled allocation successful.
>(II) intel(0): Page Flipping disabled
>(II) intel(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000
>(II) UXA(0): Driver registered support for the following operations:
>(II)         solid
>(II)         copy
>(II)         composite (RENDER acceleration)
>(==) intel(0): Backing store disabled
>(==) intel(0): Silken mouse enabled
>(II) intel(0): Initializing HW Cursor
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): Current clock rate multiplier: 1
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 00 00 00 00 00 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 00 00 00 00 1E 00 00 00 (Success)
>(II) intel(0): Fixed memory allocation layout:
>(II) intel(0): 0x00000000-0x00000fff: power context (4 kB)
>(II) intel(0): 0x0077f000:            end of stolen memory
>(II) intel(0): 0x0077f000-0x0fffffff: DRI memory manager (254468 kB)
>(II) intel(0): 0x10000000:            end of aperture
>(II) intel(0): BO memory allocation layout:
>(II) intel(0): 0x0077f000:            start of memory manager
>(II) intel(0): 0x00800000-0x00e3ffff: front buffer (6400 kB) X tiled
>(II) intel(0): 0x0079f000-0x0079ffff: overlay registers (4 kB)
>(II) intel(0): 0x007a0000-0x007aefff: exa G965 state buffer (60 kB)
>(II) intel(0): 0x007b0000-0x007b7fff: logical 3D context (32 kB)
>(II) intel(0): 0x007b8000-0x007c1fff: HW cursors (40 kB)
>(II) intel(0): 0x10000000:            end of memory manager
>(WW) intel(0): ESR is 0x00000001
>(WW) intel(0): Existing errors found in hardware state.
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): using SSC reference clock of 100 MHz
>(II) intel(0): Mode for pipe B:
>(II) intel(0): Modeline "1280x800"x60.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): chosen: dotclock 75714 vco 2120000 ((m 106, m1 17, m2 9), n 3, (p 28, p1 2, p2 14))
>(II) intel(0): Selecting standard 18 bit TMDS pixel format.
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 491 520 -hsync -vsync (37.9 kHz)
>(II) intel(0): chosen: dotclock 31500 vco 2520000 ((m 105, m1 17, m2 8), n 2, (p 80, p1 8, p2 10))
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Hardware state at EnterVT:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>(II) intel(0):               C0DRB0: 0x000f0002 (0x0002)
>(II) intel(0):               C0DRB1: 0x0000000f (0x000f)
>(II) intel(0):               C0DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C0DRB3: 0x00c00000 (0x0000)
>(II) intel(0):               C1DRB0: 0x17cbe000 (0xe000)
>(II) intel(0):               C1DRB1: 0x000017cb (0x17cb)
>(II) intel(0):               C1DRB2: 0x00000000 (0x0000)
>(II) intel(0):               C1DRB3: 0x00000000 (0x0000)
>(II) intel(0):              C0DRA01: 0x000300c0 (0x00c0)
>(II) intel(0):              C0DRA23: 0x000c0003 (0x0003)
>(II) intel(0):              C1DRA01: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA23: 0x00000000 (0x0000)
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006800
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x20000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x0008001c (disabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00003f80
>(II) intel(0):               DSPFW1: 0x3f8f0f0f
>(II) intel(0):               DSPFW2: 0x00000f0f
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0xc2308300 (enabled, pipe B, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x0008001c (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):                 DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000003 (power target: on)
>(II) intel(0):            PP_STATUS: 0xd0000009 (on, ready, sequencing on)
>(II) intel(0):         PP_ON_DELAYS: 0x012c07d0
>(II) intel(0):        PP_OFF_DELAYS: 0x012c0bc0
>(II) intel(0):           PP_DIVISOR: 0x003e7f06
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x0f5c0ccd
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000400
>(II) intel(0):             DSPACNTR: 0x58000400 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00001400 (5120 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00800000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x00000000 (disabled, inactive)
>(II) intel(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEASTAT: 0x80000004 (status: FIFO_UNDERRUN SVBLANK_INT_STATUS)
>(II) intel(0):                 FPA0: 0x00021108 (n = 2, m1 = 17, m2 = 8)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0x14800c00 (disabled, non-dvo, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x033f027f (640 active, 832 total)
>(II) intel(0):             HBLANK_A: 0x033f027f (640 start, 832 end)
>(II) intel(0):              HSYNC_A: 0x02bf0297 (664 start, 704 end)
>(II) intel(0):             VTOTAL_A: 0x020701df (480 active, 520 total)
>(II) intel(0):             VBLANK_A: 0x020701df (480 start, 520 end)
>(II) intel(0):              VSYNC_A: 0x01ea01e8 (489 start, 491 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0xd9000400 (enabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00001400 (5120 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00800000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0xc0000000 (enabled, active)
>(II) intel(0):             PIPEBSRC: 0x04ff031f (1280, 800)
>(II) intel(0):            PIPEBSTAT: 0x80000206 (status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>(II) intel(0):                 FPB0: 0x00031109 (n = 3, m1 = 17, m2 = 9)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x98026c00 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 2, p2 = 14)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x05e704ff (1280 active, 1512 total)
>(II) intel(0):             HBLANK_B: 0x05e704ff (1280 start, 1512 end)
>(II) intel(0):              HSYNC_B: 0x056f053f (1344 start, 1392 end)
>(II) intel(0):             VTOTAL_B: 0x033f031f (800 active, 832 total)
>(II) intel(0):             VBLANK_B: 0x033f031f (800 start, 832 end)
>(II) intel(0):              VSYNC_B: 0x03280322 (803 start, 809 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x80000000 (disabled)
>(II) intel(0):               TV_CTL: 0x000c00c0
>(II) intel(0):               TV_DAC: 0x70000000
>(II) intel(0):             TV_CSC_Y: 0x0332012d
>(II) intel(0):            TV_CSC_Y2: 0x07d30104
>(II) intel(0):             TV_CSC_U: 0x0733052d
>(II) intel(0):            TV_CSC_U2: 0x05c70200
>(II) intel(0):             TV_CSC_V: 0x0340030c
>(II) intel(0):            TV_CSC_V2: 0x06d00200
>(II) intel(0):         TV_CLR_KNOBS: 0x00404000
>(II) intel(0):         TV_CLR_LEVEL: 0x010b00e1
>(II) intel(0):           TV_H_CTL_1: 0x00400359
>(II) intel(0):           TV_H_CTL_2: 0x80480022
>(II) intel(0):           TV_H_CTL_3: 0x007c0344
>(II) intel(0):           TV_V_CTL_1: 0x00f01415
>(II) intel(0):           TV_V_CTL_2: 0x00060607
>(II) intel(0):           TV_V_CTL_3: 0x80120001
>(II) intel(0):           TV_V_CTL_4: 0x000900f0
>(II) intel(0):           TV_V_CTL_5: 0x000a00f0
>(II) intel(0):           TV_V_CTL_6: 0x000900f0
>(II) intel(0):           TV_V_CTL_7: 0x000a00f0
>(II) intel(0):          TV_SC_CTL_1: 0xc1710087
>(II) intel(0):          TV_SC_CTL_2: 0x6b405140
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00360024
>(II) intel(0):          TV_WIN_SIZE: 0x02640198
>(II) intel(0):      TV_FILTER_CTL_1: 0x8000085e
>(II) intel(0):      TV_FILTER_CTL_2: 0x00012d2d
>(II) intel(0):      TV_FILTER_CTL_3: 0x00009696
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0xb1403000
>(II) intel(0):         TV_H_LUMA_59: 0x0000b060
>(II) intel(0):        TV_H_CHROMA_0: 0xb1403000
>(II) intel(0):       TV_H_CHROMA_59: 0x0000b060
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x20000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000044
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):        FENCE START 0: 0x0080009d ( enabled, X tile walk, 4992 pitch, 0x00800000 start)
>(II) intel(0):          FENCE END 0: 0x00e3f000 (                                   0x00e3f000 end)
>(II) intel(0):        FENCE START 1: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 1: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 2: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 2: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 3: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 3: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 4: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 4: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 5: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 5: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 6: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 6: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 7: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 7: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 8: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 8: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):        FENCE START 9: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):          FENCE END 9: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 10: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 10: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 11: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 11: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 12: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 12: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 13: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 13: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 14: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 14: 0x00000000 (                                   0x00000000 end)
>(II) intel(0):       FENCE START 15: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II) intel(0):         FENCE END 15: 0x00000000 (                                   0x00000000 end)
>(II) intel(0): pipe A dot 31500 n 2 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): pipe B dot 75714 n 3 m1 17 m2 9 p1 2 p2 14
>(II) intel(0): DumpRegsEnd
>(II) intel(0): Output configuration:
>(II) intel(0):   Pipe A is off
>(II) intel(0):   Display plane A is now disabled and connected to pipe A.
>(II) intel(0):   Pipe B is on
>(II) intel(0):   Display plane B is now enabled and connected to pipe B.
>(II) intel(0):   Output VGA is connected to pipe none
>(II) intel(0):   Output LVDS is connected to pipe B
>(II) intel(0):   Output TMDS-1 is connected to pipe none
>(II) intel(0):   Output TV is connected to pipe none
>(II) intel(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>(II) intel(0): DPMS enabled
>(==) intel(0): Intel XvMC decoder disabled
>(II) intel(0): Set up textured video
>(II) intel(0): Set up overlay video
>(II) intel(0): direct rendering: DRI2 Enabled
>(--) RandR disabled
>(II) Initializing built-in extension Generic Event Extension
>(II) Initializing built-in extension SHAPE
>(II) Initializing built-in extension MIT-SHM
>(II) Initializing built-in extension XInputExtension
>(II) Initializing built-in extension XTEST
>(II) Initializing built-in extension BIG-REQUESTS
>(II) Initializing built-in extension SYNC
>(II) Initializing built-in extension XKEYBOARD
>(II) Initializing built-in extension XC-MISC
>(II) Initializing built-in extension XINERAMA
>(II) Initializing built-in extension XFIXES
>(II) Initializing built-in extension RENDER
>(II) Initializing built-in extension RANDR
>(II) Initializing built-in extension COMPOSITE
>(II) Initializing built-in extension DAMAGE
>(II) AIGLX: enabled GLX_MESA_copy_sub_buffer
>(II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control
>(II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects
>(II) AIGLX: Loaded and initialized /usr/lib/xorg/modules/dri/i965_dri.so
>(II) GLX: Initialized DRI2 GL provider for screen 0
>(II) intel(0): Setting screen physical size to 331 x 207
>(EE) intel(0): underrun on pipe B!
>(II) config/hal: Adding input device AlpsPS/2 ALPS GlidePoint
>(II) LoadModule: "synaptics"
>(II) Loading /usr/lib/xorg/modules/input//synaptics_drv.so
>(II) Module synaptics: vendor="X.Org Foundation"
>	compiled for 1.5.99.2, module version = 0.15.2
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 4.0
>(II) Synaptics touchpad driver version 0.15.2
>(**) Option "Device" "/dev/input/event3"
>(II) AlpsPS/2 ALPS GlidePoint: x-axis range 0 - 1023
>(II) AlpsPS/2 ALPS GlidePoint: y-axis range 0 - 767
>(II) AlpsPS/2 ALPS GlidePoint: pressure range 0 - 127
>(II) AlpsPS/2 ALPS GlidePoint: finger width range 0 - 0
>(II) AlpsPS/2 ALPS GlidePoint: buttons: left right middle
>(**) Option "SHMConfig" "true"
>(**) Option "LeftEdge" "130"
>(**) Option "RightEdge" "840"
>(**) Option "TopEdge" "130"
>(**) Option "BottomEdge" "640"
>(**) Option "FingerLow" "7"
>(**) Option "FingerHigh" "8"
>(**) Option "MaxTapTime" "300"
>(**) Option "MaxTapMove" "110"
>(**) Option "EmulateMidButtonTime" "75"
>(**) Option "VertScrollDelta" "20"
>(**) Option "HorizScrollDelta" "20"
>(**) Option "VertTwoFingerScroll" "true"
>(**) Option "HorizTwoFingerScroll" "true"
>(**) Option "EdgeMotionMinSpeed" "200"
>(**) Option "EdgeMotionMaxSpeed" "200"
>(**) Option "UpDownScrolling" "1"
>(**) Option "CircularScrolling" "1"
>(**) Option "CircScrollTrigger" "2"
>(--) AlpsPS/2 ALPS GlidePoint touchpad found
>(**) AlpsPS/2 ALPS GlidePoint: always reports core events
>(II) XINPUT: Adding extended input device "AlpsPS/2 ALPS GlidePoint" (type: TOUCHPAD)
>(**) AlpsPS/2 ALPS GlidePoint: (accel) keeping acceleration scheme 1
>(**) AlpsPS/2 ALPS GlidePoint: (accel) filter chain progression: 2.00
>(**) AlpsPS/2 ALPS GlidePoint: (accel) filter stage 0: 20.00 ms
>(**) AlpsPS/2 ALPS GlidePoint: (accel) set acceleration profile 0
>(--) AlpsPS/2 ALPS GlidePoint touchpad found
>(II) config/hal: Adding input device PS/2 Mouse
>(II) LoadModule: "evdev"
>(II) Loading /usr/lib/xorg/modules/input//evdev_drv.so
>(II) Module evdev: vendor="X.Org Foundation"
>	compiled for 1.5.99.2, module version = 2.1.99
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 4.0
>(**) PS/2 Mouse: always reports core events
>(**) PS/2 Mouse: Device: "/dev/input/event2"
>(II) PS/2 Mouse: Found 3 mouse buttons
>(II) PS/2 Mouse: Found x and y relative axes
>(II) PS/2 Mouse: Configuring as mouse
>(**) PS/2 Mouse: YAxisMapping: buttons 4 and 5
>(**) PS/2 Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>(II) XINPUT: Adding extended input device "PS/2 Mouse" (type: MOUSE)
>(**) PS/2 Mouse: (accel) keeping acceleration scheme 1
>(**) PS/2 Mouse: (accel) filter chain progression: 2.00
>(**) PS/2 Mouse: (accel) filter stage 0: 20.00 ms
>(**) PS/2 Mouse: (accel) set acceleration profile 0
>(II) config/hal: Adding input device AT Translated Set 2 keyboard
>(**) AT Translated Set 2 keyboard: always reports core events
>(**) AT Translated Set 2 keyboard: Device: "/dev/input/event1"
>(II) AT Translated Set 2 keyboard: Found keys
>(II) AT Translated Set 2 keyboard: Configuring as keyboard
>(II) XINPUT: Adding extended input device "AT Translated Set 2 keyboard" (type: KEYBOARD)
>(**) Option "xkb_rules" "evdev"
>(**) AT Translated Set 2 keyboard: xkb_rules: "evdev"
>(**) Option "xkb_model" "evdev"
>(**) AT Translated Set 2 keyboard: xkb_model: "evdev"
>(**) Option "xkb_layout" "tr"
>(**) AT Translated Set 2 keyboard: xkb_layout: "tr"
>(**) Option "xkb_variant" "basic"
>(**) AT Translated Set 2 keyboard: xkb_variant: "basic"
>(II) config/hal: Adding input device Logitech USB RECEIVER
>(**) Logitech USB RECEIVER: always reports core events
>(**) Logitech USB RECEIVER: Device: "/dev/input/event4"
>(II) Logitech USB RECEIVER: Found 16 mouse buttons
>(II) Logitech USB RECEIVER: Found x and y relative axes
>(II) Logitech USB RECEIVER: Found scroll wheel(s)
>(II) Logitech USB RECEIVER: Configuring as mouse
>(**) Logitech USB RECEIVER: YAxisMapping: buttons 4 and 5
>(**) Logitech USB RECEIVER: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>(II) XINPUT: Adding extended input device "Logitech USB RECEIVER" (type: MOUSE)
>(**) Logitech USB RECEIVER: (accel) keeping acceleration scheme 1
>(**) Logitech USB RECEIVER: (accel) filter chain progression: 2.00
>(**) Logitech USB RECEIVER: (accel) filter stage 0: 20.00 ms
>(**) Logitech USB RECEIVER: (accel) set acceleration profile 0
>(II) config/hal: Adding input device Video Bus
>(**) Video Bus: always reports core events
>(**) Video Bus: Device: "/dev/input/event9"
>(II) Video Bus: Found keys
>(II) Video Bus: Configuring as keyboard
>(II) XINPUT: Adding extended input device "Video Bus" (type: KEYBOARD)
>(**) Option "xkb_rules" "evdev"
>(**) Video Bus: xkb_rules: "evdev"
>(**) Option "xkb_model" "evdev"
>(**) Video Bus: xkb_model: "evdev"
>(**) Option "xkb_layout" "tr"
>(**) Video Bus: xkb_layout: "tr"
>(**) Option "xkb_variant" "basic"
>(**) Video Bus: xkb_variant: "basic"
>(II) config/hal: Adding input device Video Bus
>(**) Video Bus: always reports core events
>(**) Video Bus: Device: "/dev/input/event8"
>(II) Video Bus: Found keys
>(II) Video Bus: Configuring as keyboard
>(II) XINPUT: Adding extended input device "Video Bus" (type: KEYBOARD)
>(**) Option "xkb_rules" "evdev"
>(**) Video Bus: xkb_rules: "evdev"
>(**) Option "xkb_model" "evdev"
>(**) Video Bus: xkb_model: "evdev"
>(**) Option "xkb_layout" "tr"
>(**) Video Bus: xkb_layout: "tr"
>(**) Option "xkb_variant" "basic"
>(**) Video Bus: xkb_variant: "basic"
>(II) intel(0): EDID for output VGA
>(II) intel(0): LID switch detect open with ACPI button
>(II) intel(0): EDID for output LVDS
>(II) intel(0): Manufacturer: LPL  Model: 301  Serial#: 0
>(II) intel(0): Year: 2007  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 33  vert.: 21
>(II) intel(0): Gamma: 2.20
>(II) intel(0): No DPMS capabilities specified
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.600 redY: 0.351   greenX: 0.324 greenY: 0.554
>(II) intel(0): blueX: 0.153 blueY: 0.145   whiteX: 0.312 whiteY: 0.328
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0):  W654G154W01
>(II) intel(0):  $2=Eh§ÿ
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff00320c010300000000
>(II) intel(0): 	00110103802115780ab3409959538d27
>(II) intel(0): 	25505400000001010101010101010101
>(II) intel(0): 	0101010101017e1d00e8502020304030
>(II) intel(0): 	36004bcf100000197e1d00e850202030
>(II) intel(0): 	403036004bcf10000000000000fe0057
>(II) intel(0): 	36353447803135345730310a000000fe
>(II) intel(0): 	0024323d45688ba7ff01010a202000a1
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing DDC gathered Modelines:
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing probed modes for output LVDS
>(II) intel(0): Modeline "1280x800"x60.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  107.52  1280 1368 1496 1712  1024 1027 1034 1104 (62.8 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  108.00  1280 1368 1496 1712  1024 1027 1034 1104 (63.1 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>(II) intel(0): No TV connection detected
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): EDID for output TV
>(EE) intel(0): underrun on pipe B!
>(II) intel(0): EDID for output VGA
>(II) intel(0): LID switch detect open with ACPI button
>(II) intel(0): EDID for output LVDS
>(II) intel(0): Manufacturer: LPL  Model: 301  Serial#: 0
>(II) intel(0): Year: 2007  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 33  vert.: 21
>(II) intel(0): Gamma: 2.20
>(II) intel(0): No DPMS capabilities specified
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.600 redY: 0.351   greenX: 0.324 greenY: 0.554
>(II) intel(0): blueX: 0.153 blueY: 0.145   whiteX: 0.312 whiteY: 0.328
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0):  W654G154W01
>(II) intel(0):  $2=Eh§ÿ
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff00320c010300000000
>(II) intel(0): 	00110103802115780ab3409959538d27
>(II) intel(0): 	25505400000001010101010101010101
>(II) intel(0): 	0101010101017e1d00e8502020304030
>(II) intel(0): 	36004bcf100000197e1d00e850202030
>(II) intel(0): 	403036004bcf10000000000000fe0057
>(II) intel(0): 	36353447803135345730310a000000fe
>(II) intel(0): 	0024323d45688ba7ff01010a202000a1
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing DDC gathered Modelines:
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing probed modes for output LVDS
>(II) intel(0): Modeline "1280x800"x60.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  107.52  1280 1368 1496 1712  1024 1027 1034 1104 (62.8 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  108.00  1280 1368 1496 1712  1024 1027 1034 1104 (63.1 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>(II) intel(0): No TV connection detected
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): EDID for output TV
>(II) intel(0): EDID for output VGA
>(II) intel(0): LID switch detect open with ACPI button
>(II) intel(0): EDID for output LVDS
>(II) intel(0): Manufacturer: LPL  Model: 301  Serial#: 0
>(II) intel(0): Year: 2007  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 33  vert.: 21
>(II) intel(0): Gamma: 2.20
>(II) intel(0): No DPMS capabilities specified
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.600 redY: 0.351   greenX: 0.324 greenY: 0.554
>(II) intel(0): blueX: 0.153 blueY: 0.145   whiteX: 0.312 whiteY: 0.328
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0):  W654G154W01
>(II) intel(0):  $2=Eh§ÿ
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff00320c010300000000
>(II) intel(0): 	00110103802115780ab3409959538d27
>(II) intel(0): 	25505400000001010101010101010101
>(II) intel(0): 	0101010101017e1d00e8502020304030
>(II) intel(0): 	36004bcf100000197e1d00e850202030
>(II) intel(0): 	403036004bcf10000000000000fe0057
>(II) intel(0): 	36353447803135345730310a000000fe
>(II) intel(0): 	0024323d45688ba7ff01010a202000a1
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing DDC gathered Modelines:
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing probed modes for output LVDS
>(II) intel(0): Modeline "1280x800"x60.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  107.52  1280 1368 1496 1712  1024 1027 1034 1104 (62.8 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  108.00  1280 1368 1496 1712  1024 1027 1034 1104 (63.1 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>(II) intel(0): No TV connection detected
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): EDID for output TV
>(II) intel(0): EDID for output VGA
>(II) intel(0): LID switch detect open with ACPI button
>(II) intel(0): EDID for output LVDS
>(II) intel(0): Manufacturer: LPL  Model: 301  Serial#: 0
>(II) intel(0): Year: 2007  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 33  vert.: 21
>(II) intel(0): Gamma: 2.20
>(II) intel(0): No DPMS capabilities specified
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.600 redY: 0.351   greenX: 0.324 greenY: 0.554
>(II) intel(0): blueX: 0.153 blueY: 0.145   whiteX: 0.312 whiteY: 0.328
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0):  W654G154W01
>(II) intel(0):  $2=Eh§ÿ
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff00320c010300000000
>(II) intel(0): 	00110103802115780ab3409959538d27
>(II) intel(0): 	25505400000001010101010101010101
>(II) intel(0): 	0101010101017e1d00e8502020304030
>(II) intel(0): 	36004bcf100000197e1d00e850202030
>(II) intel(0): 	403036004bcf10000000000000fe0057
>(II) intel(0): 	36353447803135345730310a000000fe
>(II) intel(0): 	0024323d45688ba7ff01010a202000a1
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing DDC gathered Modelines:
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing probed modes for output LVDS
>(II) intel(0): Modeline "1280x800"x60.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  107.52  1280 1368 1496 1712  1024 1027 1034 1104 (62.8 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  108.00  1280 1368 1496 1712  1024 1027 1034 1104 (63.1 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>(II) intel(0): No TV connection detected
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): EDID for output TV
>(II) intel(0): EDID for output VGA
>(II) intel(0): LID switch detect open with ACPI button
>(II) intel(0): EDID for output LVDS
>(II) intel(0): Manufacturer: LPL  Model: 301  Serial#: 0
>(II) intel(0): Year: 2007  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 33  vert.: 21
>(II) intel(0): Gamma: 2.20
>(II) intel(0): No DPMS capabilities specified
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.600 redY: 0.351   greenX: 0.324 greenY: 0.554
>(II) intel(0): blueX: 0.153 blueY: 0.145   whiteX: 0.312 whiteY: 0.328
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0):  W654G154W01
>(II) intel(0):  $2=Eh§ÿ
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff00320c010300000000
>(II) intel(0): 	00110103802115780ab3409959538d27
>(II) intel(0): 	25505400000001010101010101010101
>(II) intel(0): 	0101010101017e1d00e8502020304030
>(II) intel(0): 	36004bcf100000197e1d00e850202030
>(II) intel(0): 	403036004bcf10000000000000fe0057
>(II) intel(0): 	36353447803135345730310a000000fe
>(II) intel(0): 	0024323d45688ba7ff01010a202000a1
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing DDC gathered Modelines:
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing probed modes for output LVDS
>(II) intel(0): Modeline "1280x800"x60.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  107.52  1280 1368 1496 1712  1024 1027 1034 1104 (62.8 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  108.00  1280 1368 1496 1712  1024 1027 1034 1104 (63.1 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>(II) intel(0): No TV connection detected
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): EDID for output TV
>(II) intel(0): EDID for output VGA
>(II) intel(0): LID switch detect open with ACPI button
>(II) intel(0): EDID for output LVDS
>(II) intel(0): Manufacturer: LPL  Model: 301  Serial#: 0
>(II) intel(0): Year: 2007  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 33  vert.: 21
>(II) intel(0): Gamma: 2.20
>(II) intel(0): No DPMS capabilities specified
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.600 redY: 0.351   greenX: 0.324 greenY: 0.554
>(II) intel(0): blueX: 0.153 blueY: 0.145   whiteX: 0.312 whiteY: 0.328
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0):  W654G154W01
>(II) intel(0):  $2=Eh§ÿ
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff00320c010300000000
>(II) intel(0): 	00110103802115780ab3409959538d27
>(II) intel(0): 	25505400000001010101010101010101
>(II) intel(0): 	0101010101017e1d00e8502020304030
>(II) intel(0): 	36004bcf100000197e1d00e850202030
>(II) intel(0): 	403036004bcf10000000000000fe0057
>(II) intel(0): 	36353447803135345730310a000000fe
>(II) intel(0): 	0024323d45688ba7ff01010a202000a1
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing DDC gathered Modelines:
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing probed modes for output LVDS
>(II) intel(0): Modeline "1280x800"x60.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  107.52  1280 1368 1496 1712  1024 1027 1034 1104 (62.8 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  108.00  1280 1368 1496 1712  1024 1027 1034 1104 (63.1 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>(II) intel(0): No TV connection detected
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): EDID for output TV
>(II) intel(0): EDID for output VGA
>(II) intel(0): LID switch detect open with ACPI button
>(II) intel(0): EDID for output LVDS
>(II) intel(0): Manufacturer: LPL  Model: 301  Serial#: 0
>(II) intel(0): Year: 2007  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 33  vert.: 21
>(II) intel(0): Gamma: 2.20
>(II) intel(0): No DPMS capabilities specified
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.600 redY: 0.351   greenX: 0.324 greenY: 0.554
>(II) intel(0): blueX: 0.153 blueY: 0.145   whiteX: 0.312 whiteY: 0.328
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0):  W654G154W01
>(II) intel(0):  $2=Eh§ÿ
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff00320c010300000000
>(II) intel(0): 	00110103802115780ab3409959538d27
>(II) intel(0): 	25505400000001010101010101010101
>(II) intel(0): 	0101010101017e1d00e8502020304030
>(II) intel(0): 	36004bcf100000197e1d00e850202030
>(II) intel(0): 	403036004bcf10000000000000fe0057
>(II) intel(0): 	36353447803135345730310a000000fe
>(II) intel(0): 	0024323d45688ba7ff01010a202000a1
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing DDC gathered Modelines:
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing probed modes for output LVDS
>(II) intel(0): Modeline "1280x800"x60.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  107.52  1280 1368 1496 1712  1024 1027 1034 1104 (62.8 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  108.00  1280 1368 1496 1712  1024 1027 1034 1104 (63.1 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>(II) intel(0): No TV connection detected
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): EDID for output TV
>(II) intel(0): EDID for output VGA
>(II) intel(0): LID switch detect open with ACPI button
>(II) intel(0): EDID for output LVDS
>(II) intel(0): Manufacturer: LPL  Model: 301  Serial#: 0
>(II) intel(0): Year: 2007  Week: 0
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Digital Display Input
>(II) intel(0): Max Image Size [cm]: horiz.: 33  vert.: 21
>(II) intel(0): Gamma: 2.20
>(II) intel(0): No DPMS capabilities specified
>(II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.600 redY: 0.351   greenX: 0.324 greenY: 0.554
>(II) intel(0): blueX: 0.153 blueY: 0.145   whiteX: 0.312 whiteY: 0.328
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0): Supported additional Video Mode:
>(II) intel(0): clock: 75.5 MHz   Image Size:  331 x 207 mm
>(II) intel(0): h_active: 1280  h_sync: 1344  h_sync_end 1392 h_blank_end 1512 h_border: 0
>(II) intel(0): v_active: 800  v_sync: 803  v_sync_end 809 v_blanking: 832 v_border: 0
>(II) intel(0):  W654G154W01
>(II) intel(0):  $2=Eh§ÿ
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff00320c010300000000
>(II) intel(0): 	00110103802115780ab3409959538d27
>(II) intel(0): 	25505400000001010101010101010101
>(II) intel(0): 	0101010101017e1d00e8502020304030
>(II) intel(0): 	36004bcf100000197e1d00e850202030
>(II) intel(0): 	403036004bcf10000000000000fe0057
>(II) intel(0): 	36353447803135345730310a000000fe
>(II) intel(0): 	0024323d45688ba7ff01010a202000a1
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing DDC gathered Modelines:
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): Modeline "1280x800"x0.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): EDID vendor "LPL", prod id 769
>(II) intel(0): DDCModeFromDetailedTiming: 1280x800 Warning: We only handle separate sync.
>(II) intel(0): Printing probed modes for output LVDS
>(II) intel(0): Modeline "1280x800"x60.0   75.50  1280 1344 1392 1512  800 803 809 832 -hsync -vsync (49.9 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  107.52  1280 1368 1496 1712  1024 1027 1034 1104 (62.8 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "NTSC 480i"x0.0  108.00  1280 1368 1496 1712  1024 1027 1034 1104 (63.1 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>(II) intel(0): No TV connection detected
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): EDID for output TV

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Attachments on bug 19233: 21395 | 21401 | 21402 | 21541 | 21543 | 21843 | 21885 | 21934

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