Attachment 18178 Details for Bug 13994 – possible fix

[patch] possible fix

bug13994.diff (text/plain), 3.82 KB, created by Alex Deucher on 2008-08-07 14:19:51 UTC

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Creator: Alex Deucher

Created: 2008-08-07 14:19:51 UTC

Size: 3.82 KB

patch

obsolete

>diff --git a/src/radeon.h b/src/radeon.h
>index 8f25fdf..d53688e 100644
>--- a/src/radeon.h
>+++ b/src/radeon.h
>@@ -901,6 +901,7 @@ extern Bool RADEONGetTMDSInfoFromBIOS(xf86OutputPtr output);
> extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output);
> extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output);
> extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn);
>+extern Bool radeon_card_posted(ScrnInfoPtr pScrn);
> 
> /* radeon_commonfuncs.c */
> #ifdef XF86DRI
>diff --git a/src/radeon_bios.c b/src/radeon_bios.c
>index e8cc951..15d553f 100644
>--- a/src/radeon_bios.c
>+++ b/src/radeon_bios.c
>@@ -266,6 +266,26 @@ radeon_read_unposted_bios(ScrnInfoPtr pScrn)
>     return ret;
> }
> 
>+Bool
>+radeon_card_posted(ScrnInfoPtr pScrn)
>+{
>+    RADEONInfoPtr info     = RADEONPTR(pScrn);
>+    unsigned char *RADEONMMIO = info->MMIO;
>+    uint32_t reg;
>+
>+    if (IS_AVIVO_VARIANT) {
>+	reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL);
>+	if (reg & AVIVO_CRTC_EN)
>+	    return TRUE;
>+    } else {
>+	reg = INREG(RADEON_CRTC_GEN_CNTL) | INREG(RADEON_CRTC2_GEN_CNTL);
>+	if (reg & RADEON_CRTC_EN)
>+	    return TRUE;
>+    }
>+
>+    return FALSE;
>+}
>+
> /* Read the Video BIOS block and the FP registers (if applicable). */
> Bool
> RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr  pInt10)
>@@ -273,7 +293,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr  pInt10)
>     RADEONInfoPtr info     = RADEONPTR(pScrn);
>     int tmp;
>     unsigned short dptr;
>-    Bool unposted = FALSE;
>+    Bool posted = TRUE;
> 
> #ifdef XSERVER_LIBPCIACCESS
>     int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE;
>@@ -292,7 +312,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr  pInt10)
> 			 RADEON_VBIOS_SIZE);
> 	} else if (!radeon_read_bios(pScrn)) {
> 	    (void)radeon_read_unposted_bios(pScrn);
>-	    unposted = TRUE;
>+	    posted = FALSE;
> 	}
>     }
> 
>@@ -387,22 +407,11 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr  pInt10)
>      * so let's work around this for now by only POSTing if none of the
>      * CRTCs are enabled
>      */
>-    if (unposted && info->VBIOS) {	
>-	    unsigned char *RADEONMMIO = info->MMIO;
>-	    uint32_t reg;
>-
>-	    if (IS_AVIVO_VARIANT) {
>-		    reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL);
>-		    if (reg & AVIVO_CRTC_EN)
>-			    unposted = FALSE;
>-	    } else {
>-		    reg = INREG(RADEON_CRTC_GEN_CNTL) | INREG(RADEON_CRTC2_GEN_CNTL);
>-		    if (reg & RADEON_CRTC_EN)
>-			    unposted = FALSE;
>-	    }
>+    if ((!posted) && info->VBIOS) {
>+	posted = radeon_card_posted(pScrn);
>     }
> 
>-    if (unposted && info->VBIOS) {
>+    if ((!posted) && info->VBIOS) {
> 	if (info->IsAtomBios) {
> 	    if (!rhdAtomASICInit(info->atomBIOS))
> 		xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
>diff --git a/src/radeon_driver.c b/src/radeon_driver.c
>index 010f1b9..45d2c2f 100644
>--- a/src/radeon_driver.c
>+++ b/src/radeon_driver.c
>@@ -5384,26 +5384,18 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
> {
>     ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
>     RADEONInfoPtr  info  = RADEONPTR(pScrn);
>-    unsigned char *RADEONMMIO = info->MMIO;
>-    uint32_t mem_size;
>     xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
>     int i;
> 
>     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
> 		   "RADEONEnterVT\n");
> 
>-    if (info->ChipFamily >= CHIP_FAMILY_R600)
>-	mem_size = INREG(R600_CONFIG_MEMSIZE);
>-    else
>-	mem_size = INREG(RADEON_CONFIG_MEMSIZE);
>-
>-    if (mem_size == 0) { /* Softboot V_BIOS */
>+    if (!radeon_card_posted(pScrn)) { /* Softboot V_BIOS */
> 	if (info->IsAtomBios) {
> 	    rhdAtomASICInit(info->atomBIOS);
> 	} else {
> 	    xf86Int10InfoPtr pInt;
>-	    xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
>-		       "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n");
>+
> 	    pInt = xf86InitInt10 (info->pEnt->index);
> 	    if (pInt) {
> 		pInt->num = 0xe6;

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