Attachment 110698 Details for Bug 83677 – Add extra flush flags for gen7 invalidate

[patch] Add extra flush flags for gen7 invalidate

0001-flush-flags.patch (text/plain), 1.06 KB, created by Chris Wilson on 2014-12-10 20:56:27 UTC

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Creator: Chris Wilson

Created: 2014-12-10 20:56:27 UTC

Size: 1.06 KB

patch

obsolete

>From 068193d1934b1347637c5a556a9f02c25966a75b Mon Sep 17 00:00:00 2001
>From: root <root@localhost.localdomain>
>Date: Wed, 10 Dec 2014 13:46:30 +0000
>Subject: [PATCH 1/2] flush-flags
>
>---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>index 3887f1a..eb6e6eb 100644
>--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>@@ -373,12 +373,15 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
> 		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
> 		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
> 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
>+		flags |= 1 << 16;
> 		/*
> 		 * TLB invalidate requires a post-sync write.
> 		 */
> 		flags |= PIPE_CONTROL_QW_WRITE;
> 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> 
>+		flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
>+
> 		/* Workaround: we must issue a pipe_control with CS-stall bit
> 		 * set before a pipe_control command that has the state cache
> 		 * invalidate bit set. */
>-- 
>1.9.3
>

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Attachments on bug 83677: 105992 | 106501 | 106508 | 106519 | 106669 | 107665 | 108029 | 108310 | 108459 | 108976 | 109009 | 109018 | 109019 | 109165 | 109331 | 109459 | 110698 | 110699

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